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Tessolve Semiconductors (a venture of Hero Electronix)

Analog Layout Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS
Experience: 4 to 8 years
No of Position: 6
Location: Bangalore

Requirements:
Minimum 3+ years of Design Knowledge in CMOS lower process nodes such as 7nm/14nm/28nm.
Should have worked on Basic Building Blocks Circuit Design of Analog such as Bandgap Reference.
Current Mirrors, Sample/Hold, Comparator, Differential Amplifier, Opamp, Bias Generator,POR/BOR.
High Speed Latch,High Speed Rx Front End.
Must understand Fabrication steps, short channel effects, EM, IR Drop, RV Violations.
Must understand Matching Device Concepts, ESDS, Latup, Antenna effect, Common Centroid, Interdigitized Matching Tradeoffs.