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Xilinx

Job Description:

Responsible for performing RTL coding in Verilog
Design, implementation, test, integration and delivery of system level digital designs for FPGA blocks timing verification
Develop design specifications based on project requirements
Provide project schedule estimates, progress updates and technical risk identification
He needs to perform task of debugging design timing related issues on different FPGA families
He is required to provide adequate laboratory assistance
He is also needed to perform the work of manifold segmentation of the FPGA designs
Need to maintain an effective means of communication among intra- and inter department personals
Ensure to complete design and timing verification tasks within allotted timelines

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