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Xilinx

This exciting position is in Xilinx DCG – Alveo, Compute Platforms, and Infrastructure (ACPI) Engineering group as the Senior RTL Design Engineer. It will provide the individual with an opportunity to build a strong technical career in Xilinx next generation Hard/Soft IP Design. Join us on our journey in developing world class Soft IP solutions for the next generation of Xilinx highly flexible and adaptive FPGAs.

As an Senior RTL Design Engineer you will work as part of a team responsible for IP/Systems design focused primarily on AXI4 based solutions. RTL Design Engineers are expected to have thorough understanding of the AXI4 protocol, participate in providing inputs during solution architecture, Micro-architecting, RTL designing & developing IPs/Systems.

This position requires the individual to be creative, team-oriented, technology savvy, able to come up with real world use case scenarios for designing the solutions and ensure high quality & high performance solution delivery to customers.

For additional details and most recent updates, hit “Apply for job”