Master’s/Bachelor’s Degree in Electrical/Electronic engineering with 7-11 years of experience in package design and layout of advanced and heterogeneous packages to meet/exceed package and system electrical and thermal performances. Successful candidate would be responsible to develop new package solutions including pin-out definitions, DRD/DFM and stack-up requirements. You should also be well versed with chip-package design flow and LVS verification. This job requires excellent communication, teamwork and strong problem solving skills. You will be part of the fullchip integration team in Hyderabad, responsible for driving integration of advanced process node chiplets using InFO technology.

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