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Xilinx

Responsible to provide technical guidance to the team and coordination with integration desigers
Efficient in handling designs from across the globe
Responsible for independent planning and execution of layout for various designs in 7nm technology node and below
Experience in full chip and test chip layout
Exposure to FPGA integration is desirable
Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks
Knowledge of scripting languages like SKILL, PERL, TCL etc. is desirable
Strong problem solving skills
Excellent communication skills
Sound knowledge of pads arrangements and ESD/Latch-up requirements
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