Xilinx

Sr Layout Design Engineer:

Master’s/Bachelor’s Degree in Electrical/Electronics engineering with 7-12 years of experience in Analog Mixed Signal Layout. Successful candidate would be responsible for layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS etc. You should have worked on FinFet technology nodes on various analog mixed signal blocks such as PLL, Bandgap, ADC, DAC, SERDES, IO etc. together with fullchip integration of few devices. Engineer should be well versed with tools such as Virtuoso/XL/GXL, IC18.1, Calibre etc. You are required to work with circuit designers to meet design specifications. You are also expected to provide technical guidance to junior engineers. This job requires excellent teamwork, good communication and strong problem solving skill.

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