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Xilinx

Xilinx Hyderabad is looking for a senior self-motivated engineer to work on QoR analysis, creation of designs and timing closure for FPGAs. We are looking for smart, creative people who have a passion for solving complex problems.

The ideal candidate should have a strong background in RTL design using Verilog/VHDL and timing closure techniques with strong foundations in timing analysis & digital design. The candidate should have a solid understanding of timing constraints, RTL coding styles and applications. The candidate will be responsible for creating complex designs and will also work with customer designs and help them achieve timing closure.

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