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Xilinx

Following is the job specs :

Strong UVM/System Verilog programming skill.
Good python/perl script programming skill.
Experience with AXI4 bus protocol
Strong Verification fundamentals and strong debugging skills
Good knowledge of assertions and functional coverage coding and closure.
Good knowledge on code coverage analysis and closure.
Experience with gate level simulation, power aware simulation is a plus.
Experience of 8-11 years
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