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Xilinx

B Tech/M Tech in EC/EE with at least 4 years of experience in the field of FPGA Design and Implementation
Strong Digital fundamentals
Knowledge of Verilog, System Verilog
Hands on experience on Xilinx FPGAs, RTL design, Building designs out of Vivado and Timing analysis & closure
Tools – Vivado, Vitis/SDK
Exposure in scripting like Tcl, Python
System level understanding – Hardware and Software aspects of the system
Protocol knowledge – High speed serial protocols – preferably PCIe, CCIX/CXL, AXI, Coherency protocols – CHI/ACE
MUST HAVE: Working experience on PCIe based systems, architectures, protocol and specification understanding
Enthusiasm and adaptability to learn new protocols and complex architectures
Good debugging and problem solving skills

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