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Xilinx, Inc.

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work. We are ONEXILINX.

 

Responsible for:

 

Architecture support for various IP in our families
Including GTs (Gigabit Transceivers), Ethernet IP blocks, High Performance, DDR-Memory-Controllers
Help Circuit Design Teams with PPA tradeoffs and power density analysis and optimization
Understand and define device floorplan dependencies for these IP, based on BW requirements & data flows, interfaces with other blocks, power supply requirements, configuration requirements
Define methodology and run routing/congestion experiments to formally prove fabric performance in GT/Hard IP/Fabric subsystems
Develop test methodologies for characterizing Single Event Errors (SEE). Develop test chips to help define next gen SEE design rules
Next generation chip families and floorplans
Create device floorplans with collateral required by Planning/Marketing, Engineering (Circuit Design, Full-chip-Integration, Packaging, Test, Architecture & Technology Teams
Define, negotiate and document Floorplan rules
Plan global interfaces, signals & systems
Further development of Xilinx internal toolset to design device Floorplan, XML visualization tool
Define and document Package Plans, automation of Package Planning process

Desired skills

 

Circuit operation understanding: logic, transistors, clocking, SRAM
ULSI process understanding, transistors & metal stacks, Power/Perf/Area tradeoffs
Programming experience, Python, Perl
Cadence schematic & layout viewing & editing tools
RTL understanding
SOC design flows, STA
Some basic device physics understanding, incl Idsat/Ioff/Vt, gate/SD caps, metal RC, EM, IR, lifetime/reliability, SEU, latch-up
Hspice

Education Requirements : BSEE with 5 years of experience orĀ MSEE with 2 years of experience.