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Xilinx

Xilinx is seeking a capable and motivated RTL/ASIC design manager to lead front end design team of next generation AI Engine. You will take part in project planning and execution of silicon design of high-performance, low-power processor and accelerator IP for AI/ML applications.

Job Responsibilities

-Manage front end design team to execute on design and implementation of AI/ML accelerator/processor

-Drive key metrics and milestones to meet silicon tapeout schedule

-Review micro-architecture and design to meet architecture spec and optimize power, performance and cost

-Adapt and adjust to evolving requirements with creative and practical decisions

-Drive interaction and collaboration with architecture, verification and physical design teams to achieve high quality design

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