In this position you will join a video codec IP development team as the resident FPGA implementation, bringup, debug and timing closure expert.  Our mission at Xilinx is to develop advanced video codec IP supporting HEVC, AV1 and future standards.  The IP may be deployed on FPGA devices and boards as an end product and/or hardened for embedded applications.  You will help target this IP to current generation (Virtex Ultrascale) and next generation (Versal) FPGAs.  In the R&D stage of development you will help to test and debug designs using chipscope for signal tracing, RTL simulation, FW debugger, and other techniques.  In the product release stage you will be involved in timing closure and product release cycles.  Opportunities to expand area of involvement into writing and debugging embedded FW and/or porting designs to the Versal architecture may exist depending on project roadmap and time and ability of the candidate.

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