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Xilinx

Job Description

Be part of the IP team of next generation memory and chip-to-chip IO/PHY/PLL IPs. Key partner in the concept, architecture, design and micro-architecture phases of the IP
Participate in defining specification, testing and verification of the IP components.
Perform RTL-level design, including micro-architectural definition, of the digital portions of the IP architecture
Work closely with methodology, PD teams to implement RTL design into GDSII. Prior experience of collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts.
Drive design closure thru synthesis, static-timing analysis, logical equivalency checking. Help improve flows and scripts for such tasks
Support post-silicon product bring-up and debug, and sign-off on test-plans and characterization reports.
Design support for SOC/FPGA integration teams, system HW/SW teams, and global operations/manufacturing teams.
Setup and analysis of lint, synthesis, timing closure and DFT coverage reports
Define or participate in micro-architecture definition and drive for power, performance and area (PPA) targets/enhancements
Influence the methodology on mixed signal IP flows on simulations, timing closure. Participate in establishing CAD and design methodologies for correct by construction designs.
Support SOC/FPGA integration activities
Ability to handle multiple projects/tasks successfully
Knowledge of xDDR4-5/HBMx DRAM protocol; high-speed parallel bus and interface PHYs
Experience designing or integrating IP
Experience in high speed and low power digital design using advanced deep micron process
Experience with highly configurable designs

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