Develop Block, Sub System and Full chip Verification Environment and Test benches using SystemVerilog and Universal Verification Methodology (UVM)
Use simulation tools like Synopsys VCS, Cadence IES to test FPGA fabric and SoC
Develop sequences, tests cases, checkers, scoreboards and implement functional coverage using System Verilog and UVM
Manage Regressions, analyze coverage and debug failures using Verdi and DVE
Utilize good understanding of state of the art verification techniques like constraint random and coverage driven verification.
Develop Code to run on CPUs using programing/SW languages like C
Manage regressions and extract coverage and regression data using tools like Perl or Python
Create regressions and coverage reports and provide updates to the management
Communicate with cross functional teams on technical issues and status updates
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