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Xilinx

Signal & Power integrity analysis for die package and PCB, which includes but not limited to layout extraction, electromagnetic and HSPICE simulation to meet signal integrity & silicon noise spec and decoupling strategy and analysis.

•  Simultaneous switching noise/output (SSN or SSO) analysis for I/O power domain.  Eye diagram and jitter analysis via Chip-package-board co-simulation.

•  Optimal layer stackup & power plane assignment to minimize voltage noise.

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