We are looking for signal integrity engineer to design and analyze high speed interfaces and power distribution network. The candidate will work with other related design teams to define and design the product to meet power and high speed I/O requirements and help the lab measurement and debug.

Power integrity analysis for die package and PCB, which includes but not limited to layout extraction, electromagnetic and HSPICE simulation to meet silicon noise spec and decoupling strategy and analysis.
Simultaneous switching noise/output (SSN or SSO) analysis for I/O power domain.  Eye diagram and jitter analysis via Chip-package-board co-simulation.
Optimal layer stackup & power plane assignment to minimize voltage noise.
Special noise-sensitive power supply analysis and layout guideline.
Signal trace length matching and impact to timing.
Crosstalk analysis and reduction.
Full-wave simulation and model extraction for signal integrity and power integrity analysis

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