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Xilinx

Xilinx’s Vivado Simulator is a full feature compile code simulator available to all Xilinx users. It supports all commonly used HDL languages including Verilog, VHDL, SystemVerilog, System-C and design that is developed mixing these languages. The simulator has full UVM support has TCL frontend, Waveform Viewer and integrated debugger.

Vivado Simulator currently has a TCL and C-APIs to control. As part of this project the Intern will develop a Python frontend for Vivado Simulator.

Roles and Responsibilities:

As a part of this role the candidate’s responsibility includes

Interacting will all stakeholders to understand the requirement for the frontend. Develop a Specification Document that is approved by all Stakeholders.
The candidate will be responsible for implementing the spaced feature as a frontend of the Simulator.
The candidate will also be responsible for testing and fixes for the implemented features.
For more & updated details, hit “Apply for job”