We are looking for a Software Engineering Intern with interest in modeling power consumption of complex HW architectures. As part of the Device Power Modeling team, the candidate will take part in the definition, development, validation and release of power models and modeling tools for all of Xilinx’s All Programmable FPGAs, SoCs, 3D ICs and ACAP devices. Xilinx’s new hardware programmable SoC FPGAs and Adaptive Compute Acceleration Platform (ACAP) deliver most dynamic processor technology and are achieving record performances in Data Center, Wireless/5G, Automotive/ADAS and Emulation applications. These new applications and heterogeneous computing architecture brings in new challenges in power modeling, especially early power estimation of large scale user designs that solve complex acceleration or AI/ML problems.

The position requires strong programming fundamentals preferably in C++ and good understanding of power aspects of analog, digital and mixed signal circuits.

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