Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specification

Interact with architects and design engineers to create a comprehensive verification testplan

Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner

Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools

Debug tests with design engineers to deliver functionally correct design blocks

Identify and write coverage measures for stimulus quality improvements

Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

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