Be part of Xilinx’s analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3, …) and chip-to-chip Gbps proprietary PHY IP solutions. Responsibilities include


definition, review and sign-off on IP top level and component level specifications
AMS components circuit and layout design
Supervise pre-silicon layout, post-silicon characterization and debug.
Support product bring-up and debug , and Sign-off on test-plans and characterization reports.
Interface with SOC teams, system HW/SW teams, and global manufacturing teams.
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