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Xilinx

7+ years in Library circuit design, characterization

 

Good understanding of library characterization tool Liberate and/or Silicon Smart
Knowledge of RTL Verilog, DFT modeling
Understanding of spice netlist and extracted DSPF formats
Good understanding of design of common standard cell functionality
In-depth knowledge of timing Liberty format including Power, CCS, Variation Modeling
Understanding of various library design kit format and generation

and more…