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Xilinx

Job Description

Lead and manage a team of analog/mixed signal silicon IPs for PLL/Clocking,
Responsibilities include high level planning, work breakdown planning, tasks assignments and progress tracking, schedule and priority management, performance review, mentor, talent development, and hiring.
End-to-end ownership of PLL design and development, from concept phase to post-silicon optimization
Development of workflows and methodology for best in-class/best PPA PLL/Clocking circuits designs.
Contribute to the definition of microarchitecture and circuit architecture for the implementation of various PLL and clocking blocks.
Drive various domains (e.g. Analog Design, Digital Design, Architecture and Design Verification, Layout) across different geographies and time zones, to ensure successful cross-team engagement and high-quality execution
Ensure quality of work within schedule and mitigate overall risk
Contribute to the definition of flows that improve efficiency and quality of execution
Manage circuit verification flows to confirm design meets performance, power, reliability and timing requirements. Work closely with the mask design organization to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution

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