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Xilinx

Xilinx has an opening for a Hardware Lead Engineer in the SOC Design team. This team is designing the silicon portion of Adaptable Compute Acceleration Platform.

 

In this highly visible role, you will:

Work in a cross-functional capacity with multiple teams across geographic locations
You will be the micro-architect for new COE blocks of the SoC. This will include advanced elements such as coherent as well as non-coherent interconnects, virtualization, memory protection, advanced CPUs, H/W accelerators and more
Work closely with the main architecture team to make architectural trade-offs based on features, performance requirements and system limitations
You will be the link between the high-level Architecture and the Design teams, developing and owning the intermediate uArchitecture documentation , as well as mentoring the design engineers
Work with several verification and validation teams to help develop testbenches around the COE blocks
Collaborate with architecture to develop requirements for performance verification
Participate in silicon bring-up for COE blocks
Technical individual contributor, with the possibility of managing a small team
For additional details and most recent updates, hit “Apply for job”