Knowledge Center

Knowledge Center ➜ Technology


Verification methodology


The Universal Verification Methodology (UVM) is an open source SystemVerilog library allowing creation of reusable verification components and assembling test environments utilizing constrained random stimulus generation and functional coverage methodologies. UVM is a combined effort of designers and tool vendors, based on the successful OVM and VMM methodologies.

UVM 1.0 was released in early 2011 with a stable version (1.1) mid year. A reference implementation was available in 2012. The latest release is 1.2 which was released in June 2014.

  • Other names: Universal Verification Methodology
  • Type: EDA



We want to hear from you. If you have any comments or suggestions about this page, please send us your feedback.