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Cell-Aware Test

Fault model for faults within cells


As the industry moves to increasingly smaller geometries, the existing fault models and associated test patterns are becoming less effective for ensuring desired quality levels. Existing fault models only consider faults on cell inputs and outputs, and on the interconnect lines between these cells. A growing number of defects occur within the cell structures. With more recent fabrication technologies, the population of defects occurring within cells is significant-as much 50% of all defects. A way to generate test patterns that efficiently target potential new defects at the transistor level is required.

A recent approach, called cell-aware test, targets specific shorts, opens and other physical defects internal to each cell by modeling it at the transistor level. Analog simulations are performed to characterize the effects of potential short and open defects. Based on the analog simulation results, a cell-aware fault model is created that directs ATPG to generate patterns targeting these internal cell defects. There have been multiple studies that show that tests generated using cell-aware fault models find defects that the normal test methods miss. One such study by AMD found that after 400,000 die had been tested, 880 defective die per million passed the standard manufacturing test, but were detected by the cell-aware tests.

A key component of cell-aware test is the ability to create user-defined fault models (UDFM). UDFMs provide users the ability to define new fault models without waiting for them to be built into commercial test tools. It allows users to define the stimulus requirements that must be met in order for test patterns to detect a specific defect. The UDFM model is text based, and incorporates the standard fault models provided with ATPG tools.

Cell “MUX2” {
    Fault “Z1” {
         test { StaticFault “Z'=1;Condition “D0'=0,“D1'=0,“S'=0;}
         test { StaticFault “Z'=1;Condition “D0'=0,“D1'=1,“S'=0;}
         test { StaticFault “Z'=1;Condition “D0'=0,“D1'=0,“S'=1;}

The UDFM above specifies that ATPG must produce one of the three listed input patterns in order to detect fault Z1. This fault model provides a lot of flexibility and can specify any number of test cycles and can utilize library models, instances, and hierarchical paths within the design.

The first step is to characterize each cell in a technology library. The transistor layout for each cell, typically in GDSII format, is the starting point. An extraction tool is used to extract a transistor-level analog netlist, including parasitic capacitors and resistors. The netlist is used to identify the location of possible bridge and open defects. To model a potential cell internal bridge, the parasitic capacitor is replaced by a resistor model. Opens occur when there is a gap in a connection. In this case, a parasitic resistor that describes connectivity is replaced by a high-impedance resistor.

Analog simulation is then performed to generate the cell-aware model. The analog simulation process iteratively modifies each parasitic element in the netlist, performs the simulation, and compares the results to the fault-free analog simulation to conclude if the inserted defect is detected or not. Defects are determined as “detected” when the cell’s output voltage deviates from the “good circuit” voltage by a specified percentage (typically 50%). However, not all bridge or open defects are detected by a static change in the output voltage. Some may result in a delay in the output voltage swing. For these defects, a dual-cycle analog fault simulation is performed at-speed in order to detect even small delays.

The final process in cell-aware characterization is to convert the list of input combinations into a set of the necessary input values for each fault within each cell. Because this fault information is defined at the cell inputs as logic values, it is basically a logic fault model representation of the analog defect simulation. This set of stimulus for each cell represents the cell-aware fault model file for ATPG.

Within this file, a simulated defect (now a fault) can have one or more input combinations. An example is shown below. For this example fault ‘˜my_stuck_01’, ATPG will try to find any of the three input combinations when targeting this fault in a design. If any one of the combinations can be applied to an instance of the cell and the fault effect can be propagated to an observation point, then the fault is marked as detected for this instance; the other combinations are no longer necessary.

udfm1.0 {
    udfmtype'my_stuck_at” {

    cell “XOR2” {
        Fault “my_stuck_01” {
            Test { StaticFault “Z” = 0; Condition “A” = 0; Condition “B” = 1; }
            Test { StaticFault “Z” = 0; Condition “A” = 1; Condition “B” = 0; }
            Test { StaticFault “Z” = 1; Condition “A” = 0; Condition “B” = 0; }

Because the cell characterization process is performed for all cells within a technology library, any design using that technology can read in the same cell-aware fault model file. Characterization only needs to occur once, and can then be applied to any design using that technology node library.

Original page contents provided by Mentor Graphics