Litho Challenges Break The Design-Process Wall

The days when chip designers could throw tape “over the wall” to the manufacturing side are long gone. Over the last several technology generations, increasingly restrictive process kits have forced designers to accommodate their circuit structures to the manufacturing process.

Lacking a successor to 193nm lithography, the industry has turned to increasingly complex resolution enhancement techniques. Many formerly routine design constructs are now forbidden because of lithographic restrictions. For this reason, designers have been unable to achieve the expected area and cost reductions usually expected from new technology nodes.

In work presented at last year’s IEEE Custom Integrated Circuits Conference (CICC), J. Ryckaert and colleagues at IMEC estimated that the transition from the N28 to N20 technology node will bring a 40% increase in overall wafer cost due to the introduction of double-patterning in the back-end-of-line interconnect layers and the use of a new “middle-of-line” (MOL) device-level interconnect layer. They expect a further 12% increase with the N16 node, due to the use of finFETs, and then a dramatic 35% increase at the N10 node, thanks to the likely need for quadruple patterning of critical layers.

The increasing use of multiple exposure schemes is bringing an era of full-fledged design/technology co-optimization (DTCO). The design and process sides need to communicate from the early process development stage, while the lines between the two areas of responsibility are blurring.

Pitch, performance, and wafer cost
From the lithography perspective, it’s all about pitch. Increasing line pitch makes a design easier to print, while reducing it makes it more difficult. If a design can be printed with a single exposure, for example, it gains a substantial cost and manufacturability advantage over one that requires double patterning. Double patterning offers a similar advantage over triple or quadruple patterning. Similarly, highly repetitive patterns, like arrays of lines and spaces, are easier to print than random patterns, which why memory structures usually achieve tighter pitch than logic. Line pitch defines a number of lithography “cliffs,” beyond which a more aggressive exposure technology is needed.

Because features on the wafer are not arbitrary structures, but components of an electrical circuit, some pitch limitations are more critical than others. For example, because of the challenges of gate length scaling, a design might scale metal pitch more aggressively than contacted poly pitch. At this year’s SPIE Advanced Lithography Conference, J. Ryckaert and colleagues at IMEC presented a series of iso-area curves showing the necessary CPP as a function of metal pitch for each technology node while keeping overall area constant. For example, they estimate that the minimum pitch achievable with 193nm LE3 (litho-etch triple exposure) patterning is about 45nm. To achieve the desired scaling from N16 to N10 while avoiding the LE3 “cliff” would require a CPP pitch of 64nm and a metal pitch of 45nm.

Nor are pitch and lithography cost the only design constraints. IC manufacturers also would like to minimize overall circuit cost and maximize performance. To minimize overall process cost, designers want to minimize circuit area, maximizing the number of chips that will fit on a wafer. Often, the most space-efficient routing is two-dimensional or otherwise lithographically difficult. For example, in work presented at the 2013 IEEE CICC, Greg Yeric and colleagues at ARM noted that the 28nm node brought a requirement that all gate-level polysilicon run in a single preferred direction. This eliminated a number of common area-saving structures, including offset gate contacts and non-uniform pitch poly.

While the end of Dennard scaling has broken the direct connection between scaling and performance, every pitch specification in the circuit still carries performance implications. As discussed below, fin pitch in finFETs defines the transistor options available to designers. Larger devices, generally speaking, have longer wires, and longer wires are slower. However, it is not enough for designers to balance the area advantages of tighter pitch against the disadvantages of multiple exposures. Different approaches to multiple patterning have advantages and disadvantages, too.

All double patterning is not the same
Conceptually, the litho-etch, litho-etch (LELE) approach is the easiest to visualize. As the name implies, the pattern is created by successive lithography/etch cycles. Every feature in the circuit layer has a direct representation on a photomask. When adjacent features are too close together to print successfully, the design splits them into two separate exposures.

Despite this conceptual simplicity, the LELE scheme may not be the best choice for a given device layer. The overlay characteristics of the lithography process limit the achievable spacing between features, even when they are on different masks. Designers also must deal with “color conflicts,” where the spacing among three associated features is such that no printable “coloring” of two masks exists. Designers therefore face a choice between unpleasant alternatives. Theoretically, four “colors” are sufficient for any “map.” In lithography, though, four “colors” would equate to four exposure steps, with dramatically increased costs and reduced process margin. Nor is assigning colors in real designs straightforward. But if they can’t add a third or fourth mask, color conflicts can be resolved only by adjusting the spacing of adjacent features, which will affect the performance and area of the design. Moreover, in a complex, tightly spaced design, adjusting the position of any single feature can force a cascade of adjustments.

The alternative to LELE patterning, self-aligned double patterning (SADP), can achieve better results in some circumstances, but imposes additional challenges, too. In SADP, a spacer layer is deposited after the initial photoresist patterning step. The photoresist is removed, the spacers remain, and the result is pitch “doubling,” with two “spacer” features for every photoresist feature on the original mask. In the second lithography step, a “trim” mask is used to remove excess spacer material. For example, an SADP process might resolve a color conflict by merging two conflicting features into one on the first mask, then using the trim mask to create the desired separation between them.

An SADP design is significantly more difficult to visualize. Features will exist on the wafer that are not present on either mask, but appear only through the interactions between the masks and the lithography process. While LELE patterning is limited by the overlay between masks, SADP is constrained by CD and spacer thickness variation.

SADP is most effective with highly repetitive designs, such as arrays of lines and spaces. In a one-dimensional array, pitch doubling works as the name implies, increasing the number of lines that will fit in a given space. Duplicating two-dimensional structures in this way will not necessarily give useful results. Unfortunately, one-dimensional structures impose both an area penalty and, potentially, a performance penalty.

Because every pitch decision affects lithography cost, device cost, and device performance, neither the design side nor the process side can make decisions in isolation. The choice between a one-dimensional and a two-dimensional layout will determine which lithography process is most appropriate. Conversely, the choice of patterning strategy determines not only the design pitch, but also the layout and routing options.

FinFETs, EUV, and the future of DTCO
The introduction of finFETs adds yet another level of co-optimization. With finFETs, the transistor area is quantized: each transistor must contain an integer number of fins, and the fin height is defined by the silicon layer thickness. As a result, the transistor parameters available to designers are similarly limited. Performance can be tuned by adding or removing fins, but no finer control is possible.

It’s possible to reduce area by increasing fin height and therefore reducing the number of fins needed for a given transistor. However, doing so limits the designer’s ability to add or subtract fins and can also increase parasitic losses in the circuit. Designers must know what transistor choices are available very early in the process. Converting an existing design for planar transistors to one for a finFET process will necessarily introduce an area penalty, depending on the difference between the transistor parameters in the original design and those available in the finFET process.

Many of the co-optimization issues discussed here could be resolved by the introduction of EUV lithography. Reduce the wavelength from 193nm to 13.5nm, and multiple patterning is either not necessary at all or needed dramatically less often. Eliminating the lithography advantage that accrues to one-dimensional structures allows designers to recover the extra area such structures consume. While the per-exposure cost of EUV is likely to be high, so is the cost of any scheme requiring three or even four 193nm exposures.

Unfortunately, it remains unclear when, or even if, a production-ready EUV exposure tool will be available and what its capabilities will be. Rather, the question is whether and for how long designers can defer the decision to incorporate EUV into their designs. Given the pitch-related tradeoffs that sub-wavelength lithography requires, is it feasible to use the same design with either 193nm or EUV lithography? Or will the introduction of EUV give enough of a cost and performance improvement to justify redesigning critical layers to take advantage of it? The industry is actively considering both questions.

A future article will discuss the emerging consensus.