EUV is the clear winner down to 5nm, but what comes after that may be a combination of tools and techniques.
Chipmakers are ramping up extreme ultraviolet (EUV) lithography for advanced logic at 7nm and/or 5nm, but EUV isn’t the only lithographic option on the table.
For some time, the industry has been working on an assortment of other next-generation lithography technologies, including a new version of EUV. Each technology is different and aimed at different applications. Some are here today, while others have been stuck in R&D for years. Some may never appear.
Among the next-generation lithography tool types are:
Besides the tool types, the industry is also developing complementary patterning approaches. These approaches work with lithographic systems to create features on devices. Among them are directed self-assembly (DSA), a block co-polymer technology that assembles into patterns, and self-aligned techniques, which are used today to create fine features.
This landscape, while confusing, is important to track because some of these technologies could become critical at the most advanced nodes.
Optical to EUV to high-NA EUV
Chipmakers are banking on EUV at 7nm, 5nm and beyond for leading-edge logic, and today there are no other options available. The other next-generation lithography technologies either are not ready or not applicable at 7nm and 5nm.
What comes next is less clear. At 3nm and beyond, chipmakers hope to use high-NA EUV, but several challenges have yet to be overcome in developing this technology.
At some point, the other next-generation lithographic technologies will play a role. They are targeted for logic, memory and specialized applications.
Other options are emerging alongside of advancements in lithography, as well. The industry is putting more emphasis on advanced packaging, for example, which is another way to improve performance and reduce power. In addition, not all chips in a package need to be developed at the most advanced nodes. Using traditional optical lithography systems, analog, RF and other devices are manufactured at more mature nodes in either 200mm or 300mm fabs.
“UMC is experiencing high demand from mature 12-inch processes,” said Jason Wang, co-president of UMC, in a recent presentation. “With new applications in 5G, IoT, automotive and AI requiring these technologies, we anticipate the market conditions driving this demand to remain strong for the foreseeable future.”
Other chips will require advanced processes even with different packaging. Those include chips developed for AI devices, as well as DRAMs, FPGAs, graphics ICs and various processors.
In logic, starting at 20nm, the industry hit a speed bump. Today’s 193nm wavelength lithography, the workhorse technology in the fab, reached its limit at 40nm (20nm half-pitch). To solve that problem, the industry moved to multiple patterning techniques to continue chip scaling. This involves splitting a chip pattern into two or more simpler masks. Each mask is then printed as a separate layer.
In the fab, the most common multi-patterning techniques are called self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). This uses one lithography step, plus deposition and etch steps, to enable devices with finer pitches.
SADP, SAQP and other schemes fall under a loosely-defined category called self-aligned technologies. For years, self-aligned techniques have been used for memory, logic and other chip structures. Self-aligned techniques involve an assortment of process steps in addition to different materials.
“These material changes are in addition to the increasing use of materials for patterning in self-aligned double- or quadruple-patterning, as well as for other self-aligned structures. This includes fully self-aligned contacts or fully self-aligned vias to help deal with edge placement errors,” said Uday Mitra, vice president of strategy for etch products at Applied Materials. “For example, in a recent joint paper, Applied Materials and IBM showcased results from novel materials, thereby reducing gate resistance to a lower Vt (threshold voltage) and enabling multi-Vts. We further showed how materials engineering the source-drain extension can provide a 13% increase in effective drive current. Also, we have talked about how the use of cobalt enables continued power and performance scaling.”
Self-aligned techniques will continue to play a role in future scaling, even as the industry moves to EUV. Today, EUV lithography is ramping up at 7nm and/or 5nm. In EUV, a power source converts plasma into light at 13.5nm wavelengths, enabling 13nm resolutions. ASML’s EUV scanner makes use of a 0.33 NA lens.
Some leading-edge chips will be processed with EUV at 5nm. At this node, EUV will require some form of self-aligned techniques, such as SADP.
Nonetheless, after years of delays, EUV is finally moving from the lab to the fab. “It’s made a transition from ‘how do we make it work’ to ‘how do we make it better’,” said Dan Hutcheson, chief executive of VLSI Research. “Much of this was science before. Now it’s mostly become an engineering challenge when you move it into manufacturing.”
While chipmakers continue to bring EUV into production, ASML is working on a next-generation EUV technology called high-NA EUV. Targeted for 3nm and beyond, a high-NA EUV scanner has a 0.55 NA lens with 8nm resolutions. The first systems are slated for 2023.
High-NA EUV makes use of an anamorphic lens. By definition, an anamorphic lens produces unequal magnifications along two axes perpendicular to each other. In EUV, the two-axis lens would support 8X magnification in the scan mode and 4X in the other direction.
If today’s EUV has been difficult to develop, high-NA EUV represents a monumental challenge. “High-NA EUV is a massive engineering project,” said Chris Mack, CTO at Fractilia. “High-NA EUV is a long way in the future.”
High-NA EUV is expensive, and it has some gaps. “The value proposition for high-NA is better resolution,” said Richard Wise, technical managing director at Lam Research. “But if your resist systems are a resolution limiter anyway, the bigger scanner doesn’t buy you as much benefit. High-NA, in my mind, likely requires a significant breakthrough in resists. High-NA adoption is going to be challenged if the resists don’t improve substantially from where they are today.”
Even the current EUV resists have issues. “There hasn’t been a dramatic new solution in the last year. The workhorse for the industry is still chemically amplified resists (CAR). It has known variations. The photoacids are 3nm apart. It requires radiation chemistries with associated secondary electron diffusion. If your photoacids are 2nm to 3nm apart, we can’t expect much better than that in terms of performance, resolution and LWR. No one has found a way to break that trade off, although the industry continues to work on it,” Wise said. “Different types of resist such as metal, nanoparticles, and others have different mechanisms for photon activation. Typically, the better resolution is there in some cases, but then things like shelf life or defectivity tend to be lacking. That seems to be part of the reason why we are still using organic resists. That’s because those alternative solutions, which may have better fundamental physics, have some other challenges associated with them.”
In addition, the industry will need to re-engineer the EUV photomask at 3nm or so. In EUV, the mask is a multi-layer structure with absorbers. Based on tantalum materials, each absorber consists of a 3D-like feature that juts out on top of the mask. In operation, EUV light hits the mask at a 6º angle, with the reflections potentially causing a shadowing effect or photomask-induced imaging aberrations on the wafer. This issue is known as mask 3D effects.
One way to solve the problem is to develop EUV masks with thinner absorbers and new materials. “Mask manufacturers have been actively working with device makers to get qualified for the next technology nodes,” said Meng Lee, director of product marketing at Veeco. “We anticipate changes in the mask multi-layer and absorber materials for 3nm and beyond.”
Direct-write and nanoimprint
Meanwhile, for years, direct-write or maskless lithography was considered the ultimate technology. Originally developed by IBM in the 1980s, direct-write lithography makes use of an e-beam tool that directly patterns tiny features on a wafer.
Direct-write is attractive because it doesn’t require an expensive photomask. But the throughputs for single-beam e-beam lithography are too slow, making it too expensive for volume IC production. As a result, single-beam direct-write tools are relegated to niche applications, such as compound semiconductors and photonics.
To solve the throughput problems, the industry has been developing direct-write e-beam systems that makes use of multiple beams. At one time, several companies were developing multi-beam e-beam lithography systems, such as KLA, Mapper Lithography and Multibeam.
This technology is difficult to develop. “The real issue is throughput. Direct-write lithography, even with hundreds of thousands or even a million beams, is far too slow for wafer lithography,” Fractilia’s Mack said. “Further, there is a resolution/throughput trade-off. When printing smaller features, the direct-write tool must slow down, making throughput even worse.”
There are other issues. In 2014, for example, KLA discontinued its multi-beam lithography efforts when it couldn’t get the industry to help fund it.
Then, in 2016, Mapper rolled out a multi-beam lithography system. Mapper’s goal was to devise a 13,000-beam system. But it only managed to develop a system with 1,352 beams for a modest throughput of 1 wafer an hour.
Last year, Mapper fell into bankruptcy. ASML recently acquired Mapper’s assets. But ASML will not continue to develop Mapper’s technology.
So Multibeam appears to be the sole vendor in the multi-beam e-beam lithography market. Advantest, Vistec and others sell single-beam e-beam lithography tools.
Multibeam is developing a multi-column technology, which is targeted for two markets–lithography for low-volume IC fabrication and security. ”Multibeam made great strides last year and picked up huge momentum this year,” said David Lam, chairman and chief executive of Multibeam. “We succeeded in turning the multi-column e-beam technology into a platform spanning multiple applications, notably IC fabrication and device security. Customer activities have shifted into high gear.”
Multi-beam e-beam lithography is different than multi-beam e-beam for photomask writing. In simple terms, multi-beam mask writing involves patterning larger and more tolerant features on a mask. That’s why multi-beam mask writing has been relatively easier to develop than multi-beam direct-write.
For years, photomask makers have used single-beam e-beam systems to write patterns on a mask. Today, IMS sells a multi-beam e-beam tool for photomask writing. NuFlare is working on the technology.
“Multi-beam mask writing is being increasingly adopted as EUV goes into production. The increased demand for precision in EUV masks requires the use of slower resists. This makes multi-beam more attractive,” said Aki Fujimura, chief executive of D2S.
Perceptions on the need for multi-beam mask writing remain strong, according to a survey released by the eBeam Initiative. “The overwhelming confidence expressed in the perceptions survey for multi-beam mask writing is a positive sign for the industry, as multi-beam helps with the mask turnaround time issue, particularly for writing with slower resists and with complex mask shapes,” Fujimura said.
Meanwhile, nanoimprint lithography (NIL) is also in various stages of development. In the works since the 1990s, NIL resembles a stamping process. Initially, an e-beam system forms a pattern on a template based on a pre-defined design. Then, a separate substrate is coated with a resist. The patterned template is pressed against the substrate, forming a pattern on the substrate at feature sizes down to 5nm and beyond.
The big challenges are overlay, defectivity and throughput, which has prevented NIL from becoming a mainstream technology. “Imprint lithography is a contact-patterning method. Imprint lithography is used in applications that are defect-tolerant,” said Harry Levinson, principal at HJL Lithography, a consulting firm.
NIL is divided into two camps—memory and others. For some time, Canon has been developing an NIL system designed for the production of NAND flash and other memory types.
Toshiba, a big proponent of NIL, has used Canon’s NIL system for the production of planar NAND. Now, Canon’s system is inching towards the production of Toshiba’s 3D NAND devices.
3D NAND is the successor of planar NAND. In the 3D NAND flow, alternating layers of materials are deposited on a substrate. Then, contact or channel holes are patterned on the top. In the next step, a plasma etcher then etches tiny circular holes or channels from the top of the device stack to the bottom substrate.
To pattern the contact holes, the industry uses traditional optical lithography. Instead, Toshiba hopes to use Canon’s NIL system for contact hole patterning.
Canon’s NIL tool meets the resolution targets for Toshiba’s application. The tool has demonstrated 14nm half-pitch patterning. The system also has an 80–90 wafer per hour throughput with a 3.4nm overlay.
Fig. 1: Half-pitch 14nm resist patterns on a 300 mm wafer; (a) top-down SEM image, and (b) cross-section SEM image. Source: SK Hynix, Toshiba
There are some roadblocks. The big issue is overlay, especially near the wafer edge. “We recognize that the performance of the equipment and masks have achieved the desired target value,” said Tatsuhiko Higashiki, a senior fellow at Toshiba Memory. “We are optimizing the process integration around the wafer.”
Besides memory, NIL is being targeted for other applications. “Leading manufacturers of augmented reality devices, optical sensors and biomedical chips already are utilizing NIL and realizing the benefits of this technology, including the ability to mass manufacture micro- and nano-scale structures down to less than 40nm without restrictions to device size,” said Martin Eibelhuber, deputy head of business development at EV Group.
“Additionally, complex structures, which typically need direct writing technologies, can be replicated easily, and for many devices, the replicated layer can be directly used as a functional layer in the product. Nanoimprint resist suppliers have seen these trends and now provide polymers with a broad range of refractive indices and with an enhanced focus on high-refractive index to support the manufacture of diffractive optical elements. Thus, we expect that the nanoimprint market will grow rapidly alongside the projected rapid growth of these products,” Eibelhuber said.
Where is DSA?
DSA is also a promising technology, but the momentum has slowed due to an assortment of issues. DSA isn’t a tool technology, per se. It’s a complementary patterning approach that works with other lithography systems.
DSA enables patterns using block copolymers. In DSA, a lithography system forms a pre-defined pattern on a structure. The structure is coated with block copolymers, which then self-assemble into tiny patterns.
The problem? “Defects constitute one of the biggest challenges for enabling directed self-assembly for high-volume manufacturing. Although there have been considerable efforts to reduce defects, the level of defects in DSA has never reached a level adequate for good yield in high-volume manufacturing,” HJL’s Levinson said.
Still, Brewer Science, Imec, Leti and others are pursuing DSA. “Selective niche areas in lithography, coupled with the need for cost-savings strategies in the nanofabrication associated with bottom-up approaches to image formation, will continue to support the momentum for the use of directed self-assembly,” said Mary Ann Hockey, director of emerging technology at Brewer Science.
“Pattern rectification for high-fidelity imaging and self-alignment layers are some of the device design approaches that lend themselves to DSA patterning,” Hockey said. “However, the major challenges that require continuous improvement for DSA are similar to those for high-resolution EUV lithography. Two of these challenges are design-aware lithographic layouts, and the quality monitoring associated with achieving low levels of defectivity. In addition, etch pattern transfer using thin protective layers and post-etch line width roughness are the keys to successful implementation. With 3nm to 5nm lithography devices in discussion, it is viable that DSA could be adopted to address very specific device design requirements.”
Fig. 2: Virtual representation of block copolymers using Brewer Science’s DSA materials. Source: Brewer Science
Fig. 3: 9nm lines formed using Brewer Science’s DSA materials.
Brewer Science has demonstrated the use of DSA with EUV. “The purpose of DSA and EUV is primarily for cost savings compared to double patterning EUV,” she said. “This proof of concept research work was intended to demonstrate feasibility for cost savings and showed very equivalent final etch results to EUV single exposure. The values measured suggest that both approaches are similar for post etch critical dimensions. We believe the outcome of final etch critical dimensions are dominated by the pattern transfer steps due to the nature of multi-layer etch recipes through tri-layer material stacks.”
Clearly, several patterning options are on the table. For advanced nodes, chipmakers have bet the farm on EUV. But if EUV stumbles, the industry will find other ways to innovate. It means that chipmakers will need to put more emphasis on advanced packaging.
Of course, not all chips require EUV. Some devices will use other lithographic types. Still to be seen, however, is which ones will make it out of the lab.
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Mark, Thank you for this article which give excellent insights to the direct write EBeam Lithography challenges and history. Since ASML purchased all the patents out of the Dutch Bankruptcy in early 2019, do you see them continuing with their own Direct write EBeam effort on a limited use basis?
Peter
Hi Peter, I believe ASML discontinued Mapper’s direct-write e-beam efforts. ASML moved the people to other groups. Not sure if ASML restarted the effort. But I doubt it.