New Materials Open Door To New Devices

Integrating 2D materials into conventional semiconductor manufacturing processes may be one of the more radical changes in the chip industry’s history.

While there is pain and suffering associated with the introduction of any new materials in semiconductor manufacturing, transition metal dichalcogenides (TMDs) support a variety of new device concepts, including BEOL transistors and single-transistor logic gates. New back-gate and split-gate transistors already show the promise of 2D designs.

The advantages of TMDs like MoS₂ and WS₂ for transistor channels have been understood for some time. As devices shrink, the channel thickness also needs to shrink in order to minimize short-channel effects. In silicon, though, very thin layers suffer from reduced carrier mobility. The impact of traps and other interface defects overwhelms the bulk properties.

Two-dimensional materials, in contrast, have no out-of-plane dangling bonds, reducing or eliminating interface effects. While the industry consensus expects 3nm to be the practical thickness limit for silicon channels, a monolayer of MoS₂ is less than 1nm thick.

Until recently, contact resistance was the most significant obstacle to TMD adoption. In the last year or so, however, semimetals like antimony and bismuth have emerged as potential solutions. Semimetals tend not to create electronic states in the semiconductor band gap because they have no band gap themselves, and they have a low density of states at the Fermi level.

Still, integrating TMDs with existing semiconductor manufacturing infrastructure remains challenging. Many of the materials involved — molybdenum, sulfur, antimony, and bismuth, among others — are new to the industry and potentially detrimental to existing processes.

Making TMD monolayers
The best available TMD monolayers are made by either exfoliation from bulk material or molecular beam epitaxy on sapphire, both of which require subsequent transfer to a conventional wafer. Though it is a more manufacturing-friendly process, metal-organic chemical vapor deposition requires very high deposition temperatures and can incorporate carbon byproducts into the deposited film.

At the recent VLSI Technology Symposium, Kirby Maxey, components research engineer at Intel, and his colleagues noted there are actually two different use cases for TMD transistors. One is in the front-end-of-line, which uses TMDs to replace high-performance finFETs or silicon nanosheet transistors. This application depends on high-quality single-crystal monolayers, which at this time require deposition temperatures in the neighborhood of 1,000°C. The Intel group showed that pyrolysis of metal-organic precursor species leads to carbon deposition along with the TMD, but that alternative precursors and optimized process conditions can improve film quality.

A second potential use case places TMDs in a second (or third) active layer, stacked vertically with intervening metal and contact layers. Once metal layers are on the wafer, deposition temperatures are much more limited. But these back-end-of-line transistors are likely to be larger and able to use thicker, multicrystalline channels. A successful deposition process will need to be compatible with whatever materials are on the wafer when the deposition occurs.

Highly scaled FEOL devices seek to minimize channel thickness, with only a single monolayer of TMD material. The first nucleation sites should coalesce into a continuous film before a second layer begins to grow. In work presented at this year’s Materials Research Society Spring Meeting, researcher Songyao Tang and colleagues at RWTH Aachen University analyzed growth and coalescence of WS₂ monolayers. As the initial nucleation islands get bigger, they found that the center-to-edge distance exceeds the migration distance for adsorbed atoms. When adatoms cannot reach the edge of a crystallite, a bilayer forms. Typically, premature bilayers can cover as much as 30% of a film’s total surface area.

The RWTH Aachen University group identified several ways to reduce bilayer formation. If each individual crystallite is smaller, then adatoms don’t need to travel as far to reach the edge. So one possible solution is to reduce the grain size while increasing the number of nucleation sites. The Intel group took this idea a step further, using transition-metal-oxide patterns as a template for reaction with chalcogen precursors. With a template, process engineers can control the position and orientation of TMD grains relative to the intended circuit patterns.

Higher deposition temperatures reduce bilayer formation by increasing the distance that adatoms can migrate before being incorporated into the growing film. TMD deposition temperatures are already quite high, though, and manufacturers would like to reduce them. Finally, reducing the growth rate gives each adatom more time to find an energetically favorable location before being buried under subsequent growth.

New device designs enable new logic concepts
As proposed device designs move toward manufacturing, process engineers must determine whether a plausible integration scheme exists. For example, many proposed designs depend on a back gate, either applying a general back bias or forming individually controlled local gates. While such designs are relatively easy to fabricate by layer transfer techniques, growth of high quality TMD material directly on a preexisting gate dielectric is less straightforward.

Fig. 1: With a thick, uniform EOT that can be strongly accumulated, the full back gate configuration yields highest Ion (a); the top gate + FBG have different EOTs and are swept individually; local back gate (c) and connected dual gate (d) offer the benefit of EOT scaling. Source: Imec

In work presented at December’s IEEE Electron Device Meeting, researcher Quentin Smets and colleagues at Imec proposed four different designs — a full back gate only, a top gate plus full back gate design, a local back gate only, and a top gate plus local back gate “connected dual gate” design.[1] Of these, the connected dual gate design gave the best channel control but less consistent results. The local back gate processing caused topography in the channel. At the shortest gate lengths, a gap was present between the top gate electrode and the dielectric, possibly due to incomplete etching. These results, which were less than ideal, increase variability and offer opportunities for process improvement, but the CDG design still delivers consistently better performance.

In silicon gate-all-around designs, the whole gate is electrically a single unit. There is only one bias knob. With dual independent gates, there are two. A device with two input signals and only one output signal potentially can define a single-transistor logic gate. Conventional gates require at least two transistors. In contrast, a single-transistor gate gives the same functionality in a smaller circuit footprint. The single-transistor gate based on independently controlled top and bottom gates was first proposed in 2020 by Yun-Yan Chung and colleagues at TSMC.[2] More recently, Minjong Lee and colleagues at Inha University in South Korea demonstrated devices with a split top gate.[3] In their AND-FET transistor/gate, the two halves of the gate lie perpendicular to the channel. The transistor is “on” only if both halves of the gate are “on.” Alternatively, in the OR-FET transistor/gate, the halves of the gate are parallel to the channel. The transistor is “on” if either half of the gate is “on.”

Longitudinal and Latitudinal Split-Gate Models

Fig. 2: Images, circuit diagram, and 3D schematic top view of the AND-FET (a, b, c) and OR-FET (d, e, f). Source: Creative Commons

Conclusion
It’s too early to say if single-transistor gates based on transition metal dichalcogenides channels are the future of digital logic, or if transistors will ultimately make their way into the BEOL stack. But as the end of silicon looms — possibly for real this time — these materials offer one view of a post-silicon future.

References
[1] Q. Smets et al., “Scaling of double-gated WS2 FETs to sub-5nm physical gate length fabricated in a 300mm FAB,” 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 34.2.1-34.2.4, doi: 10.1109/IEDM19574.2021.9720517. https://ieeexplore.ieee.org/document/9720517
[2] Y. -Y. Chung et al., “Switchable NAND and NOR Logic Computing in Single Triple-Gate Monolayer MoS2 n-FET,” 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 40.3.1-40.3.4, doi: 10.1109/IEDM13553.2020.9372072.
[3] Lee, M., Park, C.Y., Hwang, D.K. et al. Longitudinal and latitudinal split-gate field-effect transistors for NAND and NOR logic circuit applications. npj 2D Mater Appl 6, 45 (2022). https://doi.org/10.1038/s41699-022-00320-w