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Next Generation Chip Embedding Technology For High Efficiency Power Modules and Power SiPs

Details of an embedded substrate process and package that uses the die‐first process sequence.

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Cost, performance, and package size are some of the key drivers required in the next generation of package interconnect and package structure evolution. Embedding active die into substrates was mainly driven by package miniaturization for communication handheld devices. However, in the case of power modules, miniaturization is not the only driver that enhances the need for embedded die substrate (EDS) packages. In this chapter, ASE Group’s trademarked embedded substrate process and package termed a‐EASI TM , which uses the die‐first process sequence, is detailed. Assembly yields is a major aspect in all chip‐embedding technologies because all the embedded die packages contain one or more known good die (KGD). Furthermore, fanout using RDL layers provides ability to integrate passives and/or active die on top of the package. This results in a very flexible heterogeneous integration for a broad set of applications including power modules and power system‐in‐packages (SiPs).

Authors
Vikas Gupta, ASE Group, Dallas, TX, USA
Kay Essig, ASE Group, Dallas, TX, USA
C.T. Chiu, ASE Group, Dallas, TX, USA
Mark Gerber, ASE Group, Dallas, TX, USA

To read more of this book chapter, click here.


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