Reducing BEOL Parasitic Capacitance Using Air Gaps

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have been proposed to create the air gap [2-3]. There are many challenges to integrate air gap in BEOL, such as process margin for un-landed vias and overall increased process complexity. In this paper, we introduce virtual fabrication as a means to study air gap process integration optimization and resulting interconnect capacitance reduction. Initial calibration to published air gap data is demonstrated.

Typical BEOL modeling utilizes idealized 2D cross-sections of metal levels and inter-level dielectric materials, with corresponding process assumption dimensions, which are then imported into a FEM solver for parasitic RC extraction. The ability to run process variations and understand the impact of specific process steps on the resulting RC extraction is limited and time consuming. The SEMulator3D virtual fabrication software platform [4] provides the capability of modeling and predicting the intricate process interactions in advanced integrated technologies while providing a built-in RC solver, which requires no mesh export, and enables faster and more predictive results. The numerical approach used in the RC solver relies on a spatial discretization which is implemented directly on the same voxel grid used for structural process modeling. This enables sub-voxel accuracy through careful adjustment of material resistivity and permittivity at material boundaries. This approach eliminates the need for generation of a boundary fitted mesh and the associated user input and computational time, enabling fast and highly reliable RC extraction. In the resistance solver, variation in material resistivity due to surface scattering at conductor surfaces is included.

Three different BEOL air gap process flows are investigated (see Fig. 1), and their electrical characteristics (Fig. 2) are correlated to published results [1-3]. Critical process steps in each of the air gap flows are identified and their impact on RC performance is discussed. The SEMulator3D virtual fabrication software platform [1] is used to model the complete BEOL air gap flows and extract parasitic RC components of each process without the burden of mesh export.

Fig. 1. SEMulator3D created air gap process flows based on published reports.

Fig. 2. Electrical correlation to published capacitance reduction for process flow AG_1, AG_2 and AG_3.

We assume a dual damascene metal process for the initial BEOL process since BEOL air gap incorporation has occurred at wider pitch (80nm and greater) metal levels.

The air gap process AG_1 is a similar process as described in [1]. It starts with metal lines being defined and subsequent process steps are used to remove the dielectric between the metal lines. The air gaps are formed by selective deposition of a protection layer, followed by dielectric deposition that ultimately “pinches-off” at the top of the metal line to form the air gap void. The resulting capacitance coupling reduction is shown in Fig. 2 and compares well to the published capacitance decrease.

BEOL process AG_2 starts by first defining the metal trenches and then using plasma damage to alter the a portion of the sidewall of the material that will ultimately serve as the dielectric isolation between metal lines. Once the damage has occurred, a sidewall protection layer (SWPL) is deposited and etched, leaving a spacer-like layer covering the damaged portion that will ultimately be removed by a HF wet etch after the metal has been deposited and polished. This AG_2 process shows the smallest capacitance reduction compared to non-air gap. Presumably, this is due to the volume of the air gap in this structure being smaller than the other options.

Finally, process AG_3, which incorporates a metal protection layer prior to creating a damaged layer between the existing metal lines, is shown in Fig. 1. The final air gap in this structure is formed post etch of the damaged region and post capping layer deposition. Both processes AG_1 and AG_3 rely on dielectric capping layer deposition which is required to “pinch-off” near the top of the metal lines. Process AG_3 also results in ~15% capacitance reduction compared to non-air gap structures.

The SEMulator3D software platform enables numerous metrology measurements, including the air gap volume measurement. The larger the air gap volume, the larger the capacitance reduction compared to non-air gap. Air gap process AG_3 is utilized in demonstrating the impact of air gap volume and capacitance reduction. AG_3 process relies on damaging the dielectric material between the metal lines in such a way as to enhance the etch characteristics of this damaged layer. The deeper and wider the damaged region, the larger the air gap volume. Fig. 3 shows the resulting AG_3 air gap volume as a function of damaged depth for three different damage processes. The resulting capacitance reduction is shown to be a linear function of air gap volume and damaged depth.

Fig. 3. Air gap volume variation and impact on structure size and capacitance reduction.

In summary, the SEMulator3D software platform has been used to demonstrate three different approaches to forming air gaps in BEOL. The complexity of each process is clearly seen in the step-by-step process description resulting from the SEMulator3D graphical output. The resulting structural differences between the three processes is also clearly understood. Finally, the parasitic RC electrical differences between the processes is also demonstrated. The capacitance advantage of incorporating air gaps in the BEOL is shown to be as large as 16%, and is clearly a function of the air gap process and ultimate air gap geometric shape and volume.

References

1. Fischer, et al, IEDM 2015, p. 5.
2. Hsien-Wei Chen, et al, IEDM 2009, p. 146.
3. Harada, et al, IEDM 2007, p. 141.
4. Coventor SEMulator3D User Guide.