Changing Direction In Chip Design

By Ed Sperling - 26 Jan, 2017 - Comments: 1

Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year's Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and ... » read more

Power Management Vs. State Machines

By Rich Wawrzyniak - 23 Jan, 2017 - Comments: 0

In the last several years, contemporary SoCs (systems-on-a-chip) have become very complex silicon solutions. They now consist of hundreds of millions of gates, 100 or more discrete Semiconductor Intellectual Property (SIP) blocks, high-speed data channels, megabytes of volatile and non-volatile embedded memory, increasing amounts of analog/mixed signal functionality, multiple CPU cores and mult... » read more

Choosing Power-Saving Techniques

By Ann Mutschler - 16 Jan, 2017 - Comments: 1

Engineers have come up with a long list of ways to save power in chip and system designs, but there are few rules to determine which approaches work best for any given design. There is widespread confusion about what techniques should be used where, which IP or subsystem is best, and how everything should be packaged together. The choices include everything from the proper level of clock and... » read more

The Power And Limits Of Money

By Gale Morrison - 11 Jan, 2017 - Comments: 0

[getperson id="11694" p_name="Wally Rhines"], CEO of [getentity id="22017" e_name="Mentor Graphics"], sat down with Semiconductor Engineering to discuss how semiconductor engineering teams make their dollars work even when budgets are limited. The issue is as important as ever, given the industry's unrelenting margin and cost pressure and the growing competition for top talent. What follows are... » read more

Era Of 3D Printing Begins

By Ed Sperling - 05 Jan, 2017 - Comments: 0

3D printing has always been an interesting side technology. It's now about to become a mainstream technology. Until recently, the majority of applications for this technology have been limited for several reasons. First, there simply isn't enough history to bet the bank on commercial manufacturing using 3D printers. The initial patent for fused deposition modeling was issued in 1986, but ... » read more

EDA, IP Up 7%

By Ed Sperling - 22 Dec, 2016 - Comments: 0

EDA and IP growth increased to $2.094 billion in Q3, a 7% gain over the $1.958 billion reported for the same period in 2015, according to just released data from the Electronic System Design Alliance Market Statistics Service. All geographic regions reported growth last quarter. So did computer-aided engineering, the largest single category, which grew 5.0% to $666.7 million in Q3, up from $... » read more

Formal’s Roadmap

By Brian Bailey - 12 Dec, 2016 - Comments: 0

Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Siemens To Buy Mentor For $4.5B

By Ed Sperling - 14 Nov, 2016 - Comments: 0

By Ed Sperling & Jeff Dorsch Siemens announced today that it has reached a deal to buy Mentor Graphics for $4.5 billion in cash. The move, if approved by regulators, would greatly expand Siemens' capabilities in multi-physics design and embedded software for everything from semiconductors to automotive wiring harnesses. The transaction is expected to close in the second quarter of 2017. Sie... » read more

Gaps In The Verification Flow

By Brian Bailey - 01 Nov, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

#54DAC: A New Beginning

By Michael MacNamara - 17 Oct, 2016 - Comments: 0

I’ve been attending DAC as an exhibitor since 1992, and serving on the executive committee since 2012. I am thrilled to serve as General Chair for the 54th iteration of this grand conference. (And no it’s not too early to think about DAC. The call for contributions is open now.) Through the years I have seen some big industry changes, most driven by the increasingly powerful tools and autom... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

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Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.