Debug: Last Bastion Of Automation

By Brian Bailey - 27 Jan, 2016 - Comments: 0

There have been a number of times when anecdotal evidence became folk law and then over time, the effort was put in to find out whether there was any truth in it. Perhaps the most famous case is the statement that verification consumes 70% of development time and resources. For years this “fact” was used in almost every verification presentation and yet nobody knew where the number had come... » read more

Tech Talk: Double-Triple Patterning

By Brian Bailey - 21 Jan, 2016 - Comments: 0

Mentor Graphics' David Abercrombie shows the differences and challenges in double patterning versus triple patterning. [youtube vid= e0wZmjBbEf0] » read more

Predictions For 2016: Markets

By Brian Bailey - 14 Jan, 2016 - Comments: 0

Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

One On One: John Lee

By Ed Sperling - 14 Jan, 2016 - Comments: 0

John Lee, general manager and vice president of Ansys—and the former CEO of data analytics firm Gear Design Solutions, which Ansys acquired in September—sat down with Semiconductor Engineering to talk about how big data techniques can be used in semiconductor and system design. What follows are excerpts of that conversation. SE: What's your goal now that Gear has been acquired by [getent... » read more

What Goes Wrong With IP

By Ed Sperling - 11 Jan, 2016 - Comments: 0

Semiconductor Engineering sat down to talk about the future of IP with Rob Aitken, R&D fellow at [getentity id="22186" comment="ARM"]; Mike Gianfagna, vice president of marketing at [getentity id="22242" e_name="eSilicon"]; Judd Heape, vice president of product applications at Apical; and Bernard Murphy, an independent industry consultant. What follows are excerpts of that discussion, which... » read more

EDA, IP Numbers Strong

By Ed Sperling - 06 Jan, 2016 - Comments: 0

EDA and IP sales were 7.1% in Q3 across all major segments and all geographical regions, increasing to $1.957 billion compared with $1.828 billion in the same period in 2014, according to just-released numbers from the EDA Consortium. The four-quarter moving average was up 8.8%. "This was an excellent quarter for EDA," said Wally Rhines, board sponsor for the EDA Consortium's Market Statisti... » read more

How To Reduce Timing Closure Headaches

By Kurt Shuler - 22 Dec, 2015 - Comments: 0

As chips have become more complex, timing closure has provided some of the most vexing challenges facing design engineers today. This step requires an increasing amount of time to complete and adds significantly to design costs and back-end schedule risks. Wire delay dominates transistor switching delay Building high-performance modern CPUs involves pipelining to achieve high frequencies. I... » read more

Intento Design

By Brian Bailey - 21 Dec, 2015 - Comments: 3

While the United States is where most EDA developments have come from, there have been pockets of success at various places around the world and one that has produced more than most in recent years in France. Semiconductor Engineering spoke with [getperson id=" 11759 " comment ="Ramy Iskander"], founder and CEO and Eric Laurent, worldwide sales and business development for [getentity id="22905"... » read more

Mobile Market Dynamics Are Changing

By Ed Sperling - 17 Dec, 2015 - Comments: 1

Ever since the introduction of the iPhone in June 2007, increasingly advanced SoCs have dominated the semiconductor supply chain, from tools to design houses to foundries. Android's introduction in 2010 only cemented the market. Together they created massive demand for power-efficient chips that were dark most of the time, feature-rich, and which could respond within milliseconds to any command... » read more

New Approaches To Low Power Design

By Ann Mutschler - 14 Dec, 2015 - Comments: 1

While Moore's Law continues to drive feature size reduction and complexity, a whole separate part of the industry is growing up around vertical markets in the IoT. While these two worlds may be different in many respects, they share one thing in common—low power design is critical to success. How engineering teams minimize power in each of these markets, and even within the same market, ca... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.