Correct-By-Design Methodology Requires Carefully Defined Constraints


Since the dawn of PCB usage, constraints have been an important part of the design. What are the dimensions? What weight of copper? Now, constraints have become much more than just physical dimensions. The most important constraints are defined by the design requirements of differential pairs, BGAs, low voltage devices, and high-speed parallel interfaces. The cost of rework skyrockets the fu... » read more

The Roadmap To 5nm


By Debra Vogler Among the challenges the semiconductor industry will be facing as it moves down the path to node 5 are resistance-capacitance (RC) management and integration. SEMI is pleased to announce a SEMICON West 2015 STS technical program exploring these and other high-volume manufacturing challenges. According to An Steegen, SVP of Process Technology at imec, the list of RC managemen... » read more

Week 48: One Week Left For Early Registration


I have to admit, writing the weekly blog has made the countdown to DAC a lot more apparent than it would have been otherwise. When I began blogging last year, I thought the watched-pot-never-boils maxim might apply, that time would drag and I’d run out of things to say months before the opening keynote. Instead, I’m fairly stunned to have just four more blogs to write until “my DAC year�... » read more

How Semiconductor IP Became Critical To SoC Design


By Mark Templeton In 1991, I had the good fortune to be a member of the founding team of Artisan Components. We started the company believing that demand was about to appear for semiconductor intellectual property. We had a few data points. We knew that before a company could start a new chip project, they first had to design and verify all kinds of generic building blocks – things like ... » read more

Problems Ahead For EDA


Semiconductor Engineering sat down with [getperson id="11411" comment="Bill Neifert"], chief technology officer at [getentity id="22521" comment="Carbon Design Systems"]; [getperson id="11032" comment="Simon Davidmann”], chief executive officer for [getentity id="22036" e_name="Imperas”]; Randy Smith, vice president of marketing for [getentity id="22605" e_name="Sonics"] and Michel Courtoy,... » read more

Tech Talk: Faster SPICE


ProPlus CTO Bruce McGaughy explains why FastSPICE (fast Simulation Program with Integrated Circuit Emphasis) is running out of steam in the finFET generation and what needs to happen next. [youtube vid=07XzUQxPUr8] » read more

Week 47: The Yin And Yang of DAC


In one of my early blog posts I explained that DAC is owned by three non-profit societies: ACM, IEEE/CEDA and EDAC. While the executive committee right now is working on a successful 52nd DAC, planning for future events has already started. Future locations are usually booked years in advance as most of convention center and hotel contracts are signed at least 18 months out. The financial liabi... » read more

Problems Ahead For EDA


You may have discovered that the Semiconductor Engineering Knowledge Center (KC) provides various ways in which data can be viewed. One way is to see what events happened in a given year. During the 1990s, company activity in terms of new startups and acquisitions reached a peak, and in 1997 there were at least 29 startups that the KC contains and 25 companies acquired (let us know if there wer... » read more

Week 46: Don’t Be Late


Last year we moved DAC’s official opening session from Tuesday to Monday. The move makes perfect sense as there is much on the Monday schedule, including tutorials as well as the designer and IP track sessions. The opening session has always been special at DAC. It is the most popular general session as various awards are given out that day too. This is how it works: Throughout the year A... » read more

Moore’s Law At 50


Moore's Law turned 50 this week…but not because of Gordon Moore. He observed that the number of transistors crammed onto a piece of silicon was doubling every 18 to 24 months and predicted that would continue to be the case. He was right, but it took many thousands of engineers who created methodologies and tools to automate the design and equipment to manufacture complex chips to make that o... » read more

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