tag: device scaling

3nm: Blurring Lines Between SoCs, PCBs And Packages
By Ann Mutschler - 02 Mar, 2020 - Comments: 5

Leading-edge chipmakers, foundries and EDA companies are pushing into 3nm and beyond, and they are encountering a long list of challenges that raise questions about whether the entire system needs to be shrunk onto a chip or into a package. For 7nm and 5nm, the problems are well understood. In fact, 5nm appears to be more of an evolution from 7nm than a major shift in direction. But at 3nm, ... » read more

Where Timing And Voltage Intersect
By Ed Sperling - 14 Feb, 2020 - Comments: 0

João Geada, chief technologist at ANSYS, talks about the limitations for power delivery networks and what processors can handle, why the current solutions to these issues are causing failures, and how voltage reduction can affect timing. » read more

Into The Cold And Darkness
By Ed Sperling - 12 Dec, 2019 - Comments: 1

The need for speed is limitless. There is far more data to process, and there is competition on a global scale to process it fastest and most efficiently. But how to achieve future revs of improvements will begin to look very different from the past. For one thing, the new criteria for that speed are frequently tied to a fixed or shrinking power budget. This is why many benchmarks these days... » read more

5nm Vs. 3nm
By Mark LaPedus - 24 Jun, 2019 - Comments: 16

Foundry vendors are readying the next wave of advanced processes, but their customers will face a myriad of confusing options—including whether to develop chips at 5nm, wait until 3nm, or opt for something in between. The path to 5nm is well-defined compared with 3nm. After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm ... » read more

Advanced Process Control
By Ed Sperling - 20 Jun, 2019 - Comments: 0

David Fried, vice president of computational products at Lam Research, looks at shrinking tolerances at advanced processes, how that affects variation in semiconductor manufacturing, and what can be done to achieve the benefits of scaling without moving to new transistor architectures. » read more

What’s the Right Path For Scaling?
By Mark LaPedus - 02 Jan, 2019 - Comments: 1

The growing challenges of traditional chip scaling at advanced nodes are prompting the industry to take a harder look at different options for future devices. Scaling is still on the list, with the industry laying plans for 5nm and beyond. But less conventional approaches are becoming more viable and gaining traction, as well, including advanced packaging and in-memory computing. Some option... » read more

Will AI Drive Scaling Forward?
By Ed Sperling - 17 Dec, 2018 - Comments: 0

The almost ubiquitous rollout of AI and its offshoots—machine learning, deep learning, neural nets of all types—will require significantly more processing power as the amount of data that needs to be processed continues to grow by orders of magnitude. What isn't clear yet is how that will affect semiconductor manufacturing or how quickly that might happen. AI is more than the latest buz... » read more

The Security Penalty
By Ed Sperling - 13 Sep, 2018 - Comments: 0

It's not clear if Meltdown, Spectre and Foreshadow caused actual security breaches, but they did prompt big processor vendors like Intel, Arm, AMD and IBM to fix these vulnerabilities before they were made public by Google's Project Zero. While all of this may make data center managers and consumers feel better in one respect, it has created a level of panic of a different sort. For decades,... » read more

Scaling Sideways
By Ed Sperling - 19 Jul, 2018 - Comments: 0

The next steps in semiconductor technology don't follow the same vectors. While 3nm chips are likely to roll out at some point in the future, it's not clear what the business case will be for developing them. What's clear is the number of companies developing chips at that node will shrink to a handful (or less), because they're going to be far too expensive to design, verify and manufacture... » read more

New Transistor Types Vs. Packaging
By Ed Sperling - 11 Jun, 2018 - Comments: 0

Plans are being formulated for the rollout of multiple types of gate-all-around FETs and literally dozens of advanced packaging options. The question now is which ones will achieve critical mass, because there aren't enough chips in the world to support all of them profitably. FinFETs, which were first introduced by Intel at 22nm, are running out of steam. While they will survive 10/7nm, and... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy