Is Art Acceptable In Verification?

By Brian Bailey - 23 Apr, 2015 - Comments: 0

The industry appears to have accepted that [getkc id="10" kc_name="verification"] involves art as well as science. This is usually based on one of three reasons, namely: the problem is large and complex; there is a lack of understanding and tools that enable it to be automated; and if it could be made a science, all of the jobs would have migrated offshore. Today, designs are built from pre-... » read more

Pressure Builds To Revamp The Design Flow

By Ed Sperling - 23 Apr, 2015 - Comments: 1

Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

Less Moore Means More Intelligence

By Brian Bailey - 23 Apr, 2015 - Comments: 3

It would seem as if the entire industry is flooding the forums with articles about [getkc id="74" comment="Moore's Law"], as it reaches its 50th birthday (April 19th) and that this represents the longest and most important exponential in the history of man. The numbers and that impact are everywhere and I do not intend to repeat them. There are lots of articles talking about when Moore’s law ... » read more

Tech Talk: Virtual Prototyping

By Brian Bailey - 22 Apr, 2015 - Comments: 0

Bill Neifert, CTO of Carbon Design Systems, talks with about the intersection of IP and EDA, driven in particular by ARM's new architecture. [youtube vid=1OopYWmRarE] » read more

FD-SOI Vs. FinFETs

By Ed Sperling - 16 Apr, 2015 - Comments: 1

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

Faster Time To Root Cause With Diagnosis-Driven Yield Analysis

By Mentor, a Siemens Business - 16 Apr, 2015 - Comments: 0

ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed... » read more

Tech Talk: Mobile Security (Part 2)

By Ed Sperling - 15 Apr, 2015 - Comments: 0

Simon Blake Wilson of Rambus' Cryptography Research Division talks about where security needs to fit into the design flow and where the biggest risks are. To view part one of this video, click here. [youtube vid=_nnniakpP3M] » read more

EDA Sets New Record

By Ed Sperling - 13 Apr, 2015 - Comments: 0

EDA revenue grew 11.9% in Q4 2014 to $2.1 billion, a new record for the industry, propelled by strong growth in both IP and physical design. On a sequential basis, that represented a 15.1% increase, while on a year-over-year basis it was 11.9%. The four-quarter moving average, which takes into account quarterly aberrations, showed a 7.3% increase. "The semiconductor industry had a strong ... » read more

Ecosystem Changes

By Ed Sperling - 07 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss changes in the semiconductor ecosystem with Kelvin Low, senior director of foundry marketing at [getentity id="22865" e_name="Samsung Semiconductor"]; John Costello, vice president of product planning at [getentity id="22849" e_name="Altera"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"], and Michiel Ligthart, p... » read more

First Time Success and Cost Control

By Brian Bailey - 01 Apr, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

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Knowledge Centers
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tag: EDA