tag: IR drop

Machine Learning for VLSI CAD: A Case Study in On-Chip Power Grid Design
By Technical Paper Link - 15 Apr, 2022 - Comments: 0

Abstract "With the improvement of VLSI technology, on-chip power grid design is becoming more challenging than before. In this design phase of VLSI CAD, power grids are generated in order to make power and ground connections to transistors or logic blocks. However, due to the scaling of supply voltage and increase in the number of transistors per unit area of the chip, power grid design has ... » read more

Overcoming The Growing Challenge Of Dynamic IR-Drop
By PV Srinivas - 24 Mar, 2022 - Comments: 0

IR-drop has always been somewhat of an issue in chip design; voltage decreases as current travels along any path with any resistance. Ohm’s Law is likely the first thing that every electrical engineer learns. But the challenges related to IR-drop (sometimes called voltage drop) have increased considerably in recent years, especially the dynamic IR-drop in the power/ground grid as circuits swi... » read more

Building Complex Chips That Last Longer
By Ed Sperling - 23 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Preventing Chips From Burning Up During Test
By Bryon Moyer - 09 Mar, 2021 - Comments: 1

It’s become increasingly difficult to manage the heat generated during IC test. Absent the proper mitigations, it’s easy to generate so much heat that probe cards and chips literally can burn up. As a result, implementing temperature-management techniques is becoming a critical part of IC testing. “We talk about systems, saying the system is good,” said Arun Krishnamoorthy, senior... » read more

PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning
By Technical Paper Link - 31 Dec, 2020 - Comments: 0

Academic research paper from Dept. of CSE, IIT Guwahatim, India. Abstract: "With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying ... » read more

Preparing For A Barrage Of Physical Effects
By Ann Mutschler - 13 Aug, 2020 - Comments: 0

Advancements in 3D transistors and packaging continue to enable better power and performance in a given footprint, but they also require more attention to physical effects stemming from both increased density and vertical stacking. Even in planar chips developed at 3nm, it will be more difficult to build both thin and thick oxide devices, which will have an impact on everything from power to... » read more

The Implementation Of Embedded In-Chip Sensing Fabrics In Today’s Cutting-Edge Technologies
By Moortec - 08 Jul, 2020 - Comments: 0

This whitepaper takes a comprehensive look at the implementation of Embedded Sensing Fabrics in today’s cutting-edge technologies and how this can benefit today’s advanced node semiconductor design engineers by improving the performance and reliability of SoC designs. With advances in CMOS technology, and the scaling of transistor channel lengths to nanometer (nm) dimensions, the density of... » read more

Lower Resistance Protects Against Failure In IC Design
By Fady Fouad - 28 May, 2020 - Comments: 0

By Fady Fouad, Esraa Swillam, and Jeff Wilson When you’re fighting off a threat, you typically want all the resistance you can muster. In IC design, on the other hand, minimizing resistance is crucial to success in power structure design. As metals get narrower with technology node advances, resistance levels rise, and voltage drop (IR) and electromigration (EM) issues grow, both in number... » read more

Reducing IR And EM Issues With Automated Via Insertion
By Mentor, a Siemens Business - 25 Mar, 2020 - Comments: 0

IR drop and EM issues are significant performance and reliability detractors at advanced nodes. Adding vias is the most effective means of correction, but traditional custom scripts are difficult and time-consuming, and do not guarantee correct-by-construction vias. The Calibre YieldEnhancer PowerVia utility uses manufacturing requirements to perform automated insertion of DRC/LVS-clean vias. R... » read more

Power Challenges In ML Processors
By Brian Bailey - 12 Mar, 2020 - Comments: 0

The design of artificial intelligence (AI) chips or machine learning (ML) systems requires that designers and architects use every trick in the book and then learn some new ones if they are to be successful. Call it style, call it architecture, there are some designs that are just better than others. When it comes to power, there are plenty of ways that small changes can make large differences.... » read more

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