Week In Review: Design, Low Power


Arm filed its registration statement for a highly anticipated IPO. Chip industry heavyweights Apple, Samsung, NVIDIA, and Intel are all expected to invest. Find the SEC filing here. Taiwan’s National Science and Technology Council (NSTC) laid out a 10-year initiative to bolster its IC design market share to 40% worldwide by 2033, with the first year’s budget of US $376 million. The sh... » read more

Power Supply Noise Effects On Jitter In Clock Synchronous Systems With Emphasis On Memory Interfaces


Power Supply Noise Effects on Jitter in Clock Synchronous Systems with Emphasis on LPDDR5X, DDR5 and HBM3 In today's fast-paced digital world, the performance and capacity of high-speed memory has become crucial for a wide range of applications, from personal computing devices to data centers and high-performance computing systems. Designers face challenges in optimizing their designs ... » read more

Week In Review: Design, Low Power


Qualcomm, NXP, Infineon, Nordic, and Bosch are jointly investing in a new RISC-V company, to be formed in Germany, that will speed up RISC-V’s adoption in commercial products. The company will be “a single source to enable compatible RISC-V based products, provide reference architectures, and help establish solutions widely used in the industry,” according to a press release. The co... » read more

Week In Review: Design, Low Power


Arm and Intel Foundry Services inked a multi-generation agreement to enable chip designers to build Arm-based SoCs on the Intel 18A process. The initial focus is mobile SoC designs, but the deal allows for potential expansion into automotive, IoT, data center, aerospace, and government applications. IFS and Arm will undertake design technology co-optimization (DTCO) to optimize chip design and ... » read more

Week In Review: Auto, Security, Pervasive Computing


Security The Biden administration released a National Cybersecurity Strategy report this week, calling on the tech community to shoulder much more responsibility, placing "responsibility on those within our digital ecosystem that are best positioned to reduce risk and shift the consequences of poor cybersecurity away from the most vulnerable in order to make our digital ecosystem more trustwor... » read more

Week In Review: Design, Low Power


Apple plans to spend an additional €1 billion (~$1.1B) over the next six years to expand its Munich, Germany-based Silicon Design Centre, including the construction of a new research facility. "The expansion of our European Silicon Design Centre will enable an even closer collaboration between our more than 2,000 engineers in Bavaria working on breakthrough innovations, including custom sil... » read more

Week in Review: Design, Low Power


Intel discontinued its Pathfinder for RISC-V program, according to numerous reports. The program provided a pre-silicon development environment to support IP selection and early-stage software development using Intel FPGA and simulator platforms. "Since Intel will not be providing any additional releases or bug fixes, we encourage you to promptly transition to third-party RISC-V software tools ... » read more

How Memory Design Optimizes System Performance


Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on the memory side. While the underlying technology still looks very familiar, the real shift is in the way those memories are connected to processing elements and various components within a syste... » read more

DDR Memory Test Challenges From DDR3 to DDR5


Cloud, networking, enterprise, high-performance computing, big data, and artificial intelligence are propelling the development of double data rate (DDR) memory chip technology. Demand for lower power requirements, higher density for more memory storage, and faster transfer speeds are constant. Servers drive the demand for next-generation DDR. Consumers benefit when existing and legacy generati... » read more

Week In Review: Design, Low Power


The U.S. Commerce Department's Bureau of Industry and Security (BIS) issued new export controls on EDA software aimed at designing gate-all-around FETs, which manufacturers plan to implement starting at 3nm (Samsung) and 2nm (Intel and TSMC). Specifically, the ruling controls export of software that is specially designed for implementing RTL to GDSII (or an equivalent standard) for GAA FET desi... » read more

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