tag: Leakage

Supply Monitoring On 28nm & FinFET: The Challenges Posed
By Ramsay Allen - 12 Apr, 2018 - Comments: 0

A Q&A with Moortec CTO Oliver King. What are the issues with supplies on advanced nodes? The supplies have been coming down, quicker than the threshold voltages which has led to less supply margin. In addition to this, the interconnects are becoming thinner and closer together, which is pushing up resistance and also capacitance. What is the effect of these issues? In short, it... » read more

UPF Power Domains And Boundaries
By Progyna Khondkar - 10 Aug, 2017 - Comments: 0

The Universal Power Format (UPF) plays a central role in mitigating dynamic and static power in the battle for low-power in advanced process technology. A higher process node is definitely attractive as more functionality integration is possible in a smaller die area at a lower cost. However, in reality, this comes at the cost of exponentially increasing leakage power. This is because the minim... » read more

The Hunt For A Low-Power PHY
By Brian Bailey - 17 Apr, 2017 - Comments: 0

Physics has been on the side of chipmakers throughout most of the lifetime of [getkc id="74" comment="Moore's Law"], but when dealing with the world outside the chip, physics is working against them. Pushing data at ever-faster rates through boards and systems consumes increasing amounts of power, but the power budget for chips has not been increasing. Could chips be constrained by their int... » read more

TFETs And/Or MOSFETs For Low-Power Design
By Katherine Derbyshire - 16 Mar, 2017 - Comments: 0

As discussed in Reducing Subthreshold Swing With TFETs, papers at December’s IEEE Electron Device Meeting examined a variety of potential designs for tunneling transistors (TFETs). That focus continued at the recent CS International Conference. In particular, Nadine Collaert discussed IMEC’s work on InGaAs homo-junction devices. Many compound semiconductor devices depend on heterojunctio... » read more

Reducing Post-Placement Leakage With Stress-Enhanced Fill Cells
By Valeriy Sukharev - 17 Mar, 2016 - Comments: 0

By Valeriy Sukharev, Jun-Ho Choy, Armen Kteyan and Henrik Hovsepyan As downward scaling of transistors continues, optimizing power consumption for mobile devices is a major concern. Power consumption consists of two components: dynamic and static. Dynamic (active) power is used while the chip is performing various functions, while static (leakage) power is consumed by leakage current (Figure... » read more

2016 And Beyond
By Krishna Balachandran - 10 Dec, 2015 - Comments: 0

Greek mythology and Roman history are replete with soothsayers, some of whom got it right and others wrong. Cassandra was cursed that her predictions wouldn’t be believed, even though she predicted the Trojan horse. Caesar’s soothsayer predicted the demise of Julius Caesar during the Ides of March, which Caesar himself was skeptical about, but indeed he was murdered before the Ides passed. ... » read more

Micro-Architectural Exploration For Low Power Design
By Abhishek Ranjan - 12 Nov, 2015 - Comments: 0

By Abishek Ranjan, Saurabh Shrimal and Sanjiv Narayan The adoption of finFET technology has created a tectonic shift in the chip design landscape. In addition to better performance (within the same power envelope) and higher reliability, finFETs have significantly reduced the leakage power at smaller technology nodes. At the same time, the share of dynamic power dissipation continues to rise... » read more

Trouble Ahead For IP industry?
By Brian Bailey - 14 May, 2015 - Comments: 0

[getkc id="106" kc_name="Power-aware design"] has risen from an afterthought to a primary design constraint for some design types. Initially it was smart phones and other battery operated devices. It has consistently expanded into additional areas including those plugged into the wall and those plugged into the grid. Some parts of the world are imposing restrictions on the power that a device c... » read more

One-On-One: Dark Possibilities
By Katherine Derbyshire - 29 Apr, 2015 - Comments: 0

Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. (P... » read more

Low Power Paradox
By Anand Iyer - 13 Mar, 2015 - Comments: 0

Power has been an important design challenge for quite some time. Leakage power started to grow in 90nm, and by 65nm it became a severe design issue. We have built many techniques to address leakage, most notably power gating. These techniques are complex and have an impact on the design as a whole. FinFET technologies are seen as a boon to this issue of leakage. There are references that qu... » read more

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