tag: mixed signal

‘Hug The Debug’ – Before It’s Too Late
By Sumit Vishwakarma - 01 Jul, 2021 - Comments: 0

Though the term “shift-left” originated in the software industry, its importance is often cited in the hardware (semiconductor) industry where the end-product (chip) costs are skyrocketing. The increase in cost is driven by a global chip shortage, especially in the automotive industry. Manufacturing a robust chip is a long, iterative process that may require many re-spins. Shift-left refers... » read more

Virtuoso ADE Assembler
By Cadence - 26 May, 2021 - Comments: 0

Cadence Virtuoso ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions. As more analysis is required, users can take incremental advantage of the Virtuoso Variation Option to do more advanced statistical analysis on the... » read more

Testing Analog Circuits Becoming More Difficult
By Susan Rambo - 11 May, 2021 - Comments: 1

Foundries and packaging houses are wrestling how to control heat in the testing phase, particularly as devices continue to shrink and as thermally sensitive analog circuits are added into SoCs and advanced packages to support everything from RF to AI. The overriding problem is that heat can damage chips or devices under test. That's certainly true for digital chips developed at advanced node... » read more

Re-Architecting SerDes
By Brian Bailey - 10 Dec, 2020 - Comments: 0

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

Brute-Force Analysis Not Keeping Up With IC Complexity
By Brian Bailey - 24 Nov, 2020 - Comments: 0

Much of the current design and verification flow was built on brute force analysis, a simple and direct approach. But that approach rarely scales, and as designs become larger and the number of interdependencies increases, ensuring the design always operates within spec is becoming a monumental task. Unless design teams want to keep adding increasing amounts of margin, they have to locate th... » read more

Mixed-Signal Methodologies: Data Management
By Cliosoft - 04 Nov, 2020 - Comments: 0

Software teams have long used version control and data management systems and they have become an integral part of a software development environment. Practically, no significant software project is started without a software data management system and methodology in place. There are a variety of solutions, typically referred to as Software Configuration Management (SCM) systems, to choose from... » read more

Increase In Analog Problems
By Brian Bailey - 19 Oct, 2020 - Comments: 6

Analog and mixed signal design has always been tough, but a resent survey suggests that the industry has seen significantly increased failures in the past year because the analog circuitry within an ASIC was out of tolerance. What is causing this spike in failures? Is it just a glitch in the data, or are these problems real? The answer is complicated, and to a large extent it depends heavily... » read more

Problems And Solutions In Analog Design
By Ann Mutschler - 05 Aug, 2020 - Comments: 1

Advanced chip design is becoming a great equalizer for analog and digital at each new node. Analog IP has more digital circuitry, and digital designs are more susceptible to kinds of noise and signal disruption that have plagued analog designs for years. This is making the design, test and packaging of SoCs much more complicated. Analog components cause the most chip production test failures... » read more

Ins And Outs Of In-Circuit Monitoring
By Ed Sperling - 21 Jul, 2020 - Comments: 2

At 7nm and 5nm, in-circuit monitoring is becoming essential. Steve Crosher, CEO of Moortec, talks about the impact of rising complexity, how different use cases and implementations can affect reliability and uptime, and why measuring electrical, voltage and thermal stress can be used to statistically predict failures and improve reliability throughout a chip’s lifetime. » read more

Fast And Accurate Variation-Aware Mixed-Signal Verification Of Time-Domain 2-Step ADC
By Mentor, a Siemens Business - 08 Jul, 2020 - Comments: 0

To meet today’s analog-to-digital converter (ADC) specifications and to produce a high-yield design, teams typically need to perform extensive brute force mixed-signal simulations to account for all potential design variation. However, at nanometer nodes, the number of process, voltage and temperature (PVT) corners and parametric variation grow exponentially making the simulation impractical ... » read more

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