Executive Insight: Jack Harding


[getperson id="11145" comment="Jack Harding"], president and CEO of [getentity id="22242" e_name="eSilicon"], sat down with Semiconductor Engineering to talk about consolidation, business relationships, what it will take to survive in the IoT age, and how to better optimize chips. What follows are excerpts of that conversation. SE: We’ve been looking at consolidation for a while and all th... » read more

Successful FlexTech Integration Providing New Opportunities for SEMI Members


By Michael Ciesinski, President, FlexTech In 2014, SEMI developed a new model – SEMI Strategic Association Partnership – for engaging other associations and organizations in a strategic, long-term relationship that supports and advances the interests of SEMI members in emerging and adjacent segments of the electronics supply chain. The strategic partner brings a community, brand, and pro... » read more

Inside The OSAT Business


Semiconductor Engineering sat down to discuss the IC-packaging industry, foundries, China and other topics with Tien Wu, chief operating officer at Taiwan's Advanced Semiconductor Engineering (ASE), the world's largest outsourced semiconductor assembly and test (OSAT) vendor. What follows are excerpts of that conversation. SE: What is your overall outlook for 2016? Wu: Last year, the semi... » read more

Inside The SRC


Semiconductor Engineering sat down to talk with Ken Hansen, the new president and chief executive of the Semiconductor Research Corp. (SRC), a U.S.-based technology research consortium. Prior to joining the SRC in May, Hansen was vice president and chief technology officer at Freescale. What follows are excerpts of that conversation. SE: My impression is that the SRC allocates funding for va... » read more

Shrinking R&D Pool


The rule of thumb in business is that consolidation in a maturing industry improves the health of the surviving companies. In most market sectors that's true. In the semiconductor industry, that formula doesn't work. The reason is due to what might well be called foundational economics. While it's possible to reduce costs in making chips for years to come, at some point the basic building bl... » read more

Manufacturing Bits: June 16


Harmonic EUV The U.S. Department of Energy’s Lawrence Berkeley National Laboratory has devised an efficient extreme ultraviolet (EUV) source. The technology could one day be used for a new class of metrology tools, based on angle-resolved photoemission spectroscopy (ARPES). This technique makes use of a photoelectric effect for studying materials. To enable the source, Berkeley Labs devel... » read more

Executive Insight: Charles Janac


SE: One of the big stories these days is consolidation. What are you seeing on your side? Janac: There are about 230 companies doing SoCs right now. Maybe 150 should be doing that. As the game gets more expensive and more difficult, some of the companies that don't have volume may have to do something else. Consolidation is part of that. But you're also going to see movement toward platforms... » read more

EDA’s Hedge Plays


While 14/16nm process technologies with finFETs and double patterning have pushed complexity to new heights, the move to 10nm fundamentally will change a number of very basic elements of the design through manufacturing flow—and EDA vendors will be caught in the middle of having to make hard choices between foundries, processes, packaging approaches, and potentially which markets to serve. ... » read more

Disruptive R&D


Leading university researchers presented their most promising technologies — describing developments ranging from sustainable metal cluster technology (that’s already spawned three notable startups) to resonance-based detection for more accurate MEMS devices — at the new Breakthrough Research Technologies session and the Silicon Innovation Forum at SEMICON West 2014. OSU metal cluster... » read more

Semiconductor R&D Crisis Ahead?


Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

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