The Analog Design Gap

By Benjamin Prautsch and Torsten Reich

Sensors are everywhere. In the context of Industry 4.0 and IoT, we face an ever-increasing demand for high-quality sensing. Data acquisition is fundamental to adaptive production chains.

So aggregating data isn’t just some nice-to-have feature. It is the basis of modern production systems. But don’t we have sensors already? Isn’t everything fine?

When collecting data from the “real world,” there is no other way than integrating analog components into Systems-on-Chip (SoC). But digital components provide a noisy environment for sensitive analog components. In addition, the design flows of both analog and digital are very different.

The digital design flow, although being far from simple push-button, is highly automated with flow components that utilize complete automation. Analog design, on the other hand, is something of an art. Just like analog designers differ, their design approaches (and also verification approaches) do, as well. These differences can be seen, for example, in the design of testbenches, the design of schematics, the affinity for whether or not they use models, the approach of how parasitic effects from the layout are estimated, as well as in the way layouts are designed.

There are numerous analog automation solutions available that address all of these challenges. There are solutions for system-level modeling—large analog and analog/mixed-signal systems can be replaced by comparably simple, yet sufficiently accurate, models to ease system design by accelerated verification. There are solutions for propagation of design data, including structural top-down requirements and design-wide constraints. And when it comes to the design of sub-components, there is research on the synthesis of analog topologies. Based on feasibility analysis, simple building blocks ranging from a few transistors down to the primitive transistor are combined based on constraints, such that the aggregated structure fulfills a predefined function like signal amplification. In this way, many topologies can be developed, and the performance of each can be stored in a library.

Speaking of libraries, we should discuss another bottleneck of design. The design of analog layouts is still manual. Digital layout synthesis relies on static standard cells, which are available for a few derivatives per technology. Analog building blocks, however, are much more diverse. Variability is required for the sizing of devices, layout concepts, as well as details of the layout. This is basically addressed by utilizing two concepts—optimization or generation. Optimization-based approaches emerged with template-based, layout-aware flows, which include all of schematic sizing, extracted estimation, layout generation, as well as layout extraction and feedback of the parasitic effects into the verification of the sized schematic. In order to create the required templates, which are abstract layout arrangements, a number of approaches were proposed. They might be classified into templates with and without routing.

An even more detailed way of abstract layout description is the generator-based approach. But generators are diverse. They also may include schematic, symbol and test bench generation. The diversity of supported semiconductor technologies strongly depends on the generator concept for layout description. Recent approaches, such as intelligent IPs, broaden the current state of the art in science and can generate cells of schematic, symbol and DRC and LVS clean layout down to 22nm. There is a good chance that even more integration is possible.

All of the tools mentioned should be used in today’s analog/mixed-signal design flows to ease the complex and complicated design procedure. There are many obstacles along the way, from system specification to the final designed system. But once analog design automation gains traction, design risk and design time will decrease significantly, and design quality will increase—and with that, so will the quality of modern products.

Torsten Reich is the group manager for Integrated Sensor Electronics at Fraunhofer IIS.