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Fraunhofer-Institut für Integrierte Schaltungen IIS, Institutsteil Entwicklung Adaptiver Systeme EAS, Dresden, Deutschland

May 2022

Reusable Analog IP – Make Your IP Intelligent with Intelligent IP (Online)

Designing analogue/mixed-signal ICs is a major challenge for ASIC development, with tight specifications and tapeout schedules that are not easy to meet. Therefore, we are continuously working on design concepts and tools that help designers with both design efficiency and risk management. In this webinar we will give you an insight into some of these solutions.

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