OneSpin Solutions’ Muhammed Haque Khan, product specialist for synthesis verification, digs into equivalence checking in FPGA designs and what can go wrong with FPGA designs.
this looks like a nice Youtube video presentation, but right in the 2nd minute it starts with false assumptions! The errors are not introduced on the arrows – except you think of manipulated bits and bytes on your file system. The errors get introduced in the boxes where the tools transform – with the help of an algorithm – an input into an output. The arrows have no algorithms nor transformation and thus they are not creating any false designs.
By assuming you can construct an equivalency checker for all steps, you’re saying you can construct a synthesizes, optimizer, placer and router, that knows all synthesis techniques, all optimization techniques, all hardware platforms of all vendors at once. So you can check, if these tools have done something wrong. Currently, there is no tool on the market that can e.g. understand VHDL 100% bug free, so why is your tool more bug free then long time existing tools?
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Hi,
this looks like a nice Youtube video presentation, but right in the 2nd minute it starts with false assumptions! The errors are not introduced on the arrows – except you think of manipulated bits and bytes on your file system. The errors get introduced in the boxes where the tools transform – with the help of an algorithm – an input into an output. The arrows have no algorithms nor transformation and thus they are not creating any false designs.
By assuming you can construct an equivalency checker for all steps, you’re saying you can construct a synthesizes, optimizer, placer and router, that knows all synthesis techniques, all optimization techniques, all hardware platforms of all vendors at once. So you can check, if these tools have done something wrong. Currently, there is no tool on the market that can e.g. understand VHDL 100% bug free, so why is your tool more bug free then long time existing tools?