Special Report
Analog’s Day Of Reckoning
Is the industry about to run out of analog designers, or will automation finally happen and increase their productivity?
Top Stories
Managing Dynamic Power
Design techniques, process flavor and power analysis all have their place in the finFET world.
SoC Integration Headaches Grow
Every chip has in-house and commercial IP, mixed signal components and a slew of tools. What’s the best way to put them together, and how do you wade through the mountains of data?
New Directions For EDA
Analysis: What was the hidden message behind DAC this year? It could just be a new EDA business model.
IP Integration Challenges Increase
Experts at the table, part 1: More characterization needed for finFET-based designs; why consolidation is both good and bad for IP vendors.
Blogs
Editor in Chief Ed Sperling digs into whether M&A activity is good for semiconductor design, in Consolidation And Innovation.
Executive Editor Ann Steffora Mutschler questions whether it’s possible to make it easier and less risky to integrate IP licensed from an outside group or company, in Reducing The Risk Of Third-Party IP Integration.
Rambus’ Loren Shalinsky observes that video and images are going to dramatically increase the amount of Internet traffic and looks at where it will all go, in Traffic Jam?
Synopsys’ Srikanth Jadcherla finds that in the IoT world, verification tools will be needed to ensure that many devices are correct by construction—and more secure, in Confidence Is The New Verification.
Mentor’s Lauro Rizzati looks at what’s needed for power analysis in million-gate SoCs, in The Old Two-Step Just Doesn’t Have That Swing.
Ansys’ Meni Jayaswal zeroes in on how to use a streaming interface with emulators, in Early Power Budgeting For Live Applications.
ARM’s Chris Shore notes that being able to map workloads to the right core sizes makes a big difference in power consumption and performance, in Not All Workloads Are Created Equal.
