Low Power-High Performance

Top Stories

Pushing Memory Harder

Can the processor/memory bottleneck be closed, or do applications need to be re-architected to avoid it?

Focus Shifts To Wasted Power

Low power is no longer enough. Is all of the power consumed usefully? Low energy is the new goal.

Using Emulators For Power/Performance Tradeoffs

Chip design's big iron is moving further forward in the design cycle.

Less Margin, More Respins, And New Markets

How physics is reshaping the leading edge of design.

More Data, More Processing, More Chips

Arm's CEO examines the impact of an explosion of data at the edge, 5G and heterogeneous architectures.

Why DRAM Won’t Go Away

New materials, new architectures and higher density have limited what can be done with DRAM, but it's still king (Experts At The Table Part 3)

FPGA Design Tradeoffs Getting Tougher

As chips grow in size, optimizing performance and power requires a bunch of new options and methodology changes.

3D Power Delivery

The design of the power delivery network just got a lot more complicated, and designers can no longer rely on margining when things become vertical.

Trading Off Power And Performance Earlier In Designs

Complexity, tighter schedules require deeper understanding throughout the design flow.

Reducing Software Power

Software plays a significant role in overall power consumption, but so far there has been little progress on that front.

More Top Stories »

Round Tables

Why DRAM Won’t Go Away

New materials, new architectures and higher density have limited what can be done with DRAM, but it's still king (Experts At The Table Part 3)

DRAM Tradeoffs: Speed Vs. Energy

Experts at the Table: Which type of DRAM is best for different applications, and why performance and power can vary so much.

HBM2 Vs. GDDR6: Tradeoffs In DRAM

Experts at the Table, part 1: Choices vary depending upon application, cost and the need for capacity and bandwidth, but the number of options is c...

Planning For 5G And The Edge

Experts at the Table, part 2: Understanding 5G's benefits, limitations and design challenges.

Process Variation And Aging

Experts at the Table, part 2: How the very fast progress of the semiconductor industry is making transistor aging even more difficult.

More Roundtables »


Making Sense Of ML Metrics

What really matters in performance/power comparisons.

Monitoring Heat On AI Chips

How to reduce margin and improve performance on very large devices.

The New CXL Standard

Why the Compute Express Link is so critical for moving large amounts of data in AI/ML applications.

Making Better Use Of Memory In AI

Rethinking number formats and precision without affecting accuracy.

Machine Learning Inferencing At The Edge

How designing ML chips differs from other types of processors.

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Latest Blogs

Editor's Note

Less Food, More Thought

Why power and performance are becoming more intertwined.
October 10, 2019
Best Of Both: LP & HP

Seeing Is Believing: Visualizing Full Coverage Closure In...

How to tackle the different coverage categories for low-power verification.
IP And LP In SoCs

Shift Left Power-Aware Static Verification

A UPF aware solution for clock and reset domain crossings.
Spotlight On Reliability

IoT For Building Energy Systems In Zero-Emission Buildings

Smart buildings lead to significant energy savings, but a few challenges remain.
Everything Low Power

Mary Jane Irwin Receives The Kaufman Award

The achievements of the first woman to receive EDA's major honor.
The Disruptive Edge

The Industrial Internet Of Things Relies On ADCs

Converting the analog information from all the sensors in a factory to the di...
At The Core

AI Warnings For Safer Driving

How real-time predictive scoring could help modify driver behavior to reduce ...
A Bit About Memory

Breaking Down The AI Memory Wall

Memory is no longer able to keep pace with raw compute capability, creating a...
September 12, 2019
Let's Talk PVT Monitoring

How To Reduce Thermal Guard-Banding

What a difference a few degrees can make.
February 14, 2019
Electromagnetic Crosstalk

How to Make Sure IP will Float in the Rough SoC Sea

The impact of coupling on designs and what to watch out for.
December 19, 2018
Power Awareness

Aging Analysis Hits Mainstream

Increasingly, the ability to address transistor aging is showing up in EDA to...
November 8, 2018

Knowledge Centers
Entities, people and technologies explored

  Trending Articles

Using Machine Learning In Fabs

ML will augment existing manufacturing processes, but it won’t replace them.

Over $7 Billion Raised In Mega-Rounds By 27 Firms

September was spectacular for startups, as 27 tech companies raised $100 million or more, taking in a total of $7.1 billion during the month.

The Race To Next-Gen 2.5D/3D Packages

New approaches aim to drive down cost, boost benefits of heterogeneous integration.

Week in Review – IoT, Security, Autos

Cadence teams with Adesto on IoT; Synopsys PrimeECO; UPS drones; FireEye for sale.

Why EV Battery Design Is So Difficult

Classic automotive design in a silo no longer works for cars that operate as electronic systems.