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Low Power-High Performance

Top Stories

RISC-V: More Than a Core

Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.

Power Issues Grow For Cloud Chips

Optimizing processor design in high-performance computing now requires lots of small changes.

Reliability, Machine Learning And Advanced Packaging

Experts at the Table, part 1: The biggest concerns in chip design and how new markets and technologies are affecting them.

Cloud Drives Changes In Network Chip Architectures

New data flow, higher switch density and IP integration create issues across the design flow.

Aging In Advanced Nodes

Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.

Enabling Cheaper Design

At what point does cheaper design enable a significant growth in custom semiconductor content? Not everyone is onboard with the idea.

Process Corner Explosion

At 7nm and below, modeling what will actually show up in silicon is a lot more complicated.

Minimizing Chip Aging Effects

Understanding aging factors within a design can help reduce the likelihood of product failures.

Variation In Low-Power FinFET Designs

Old solutions don't necessarily work anymore, particularly at advanced nodes and ultra-low voltage.

AI Architectures Must Change

Using the Von Neumann architecture for artificial intelligence applications is inefficient. What will replace it?

More Top Stories »



Round Tables

Aging In Advanced Nodes

Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.

Process Variation Not A Solved Issue

Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.

Architecting For AI

Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?

Power Modeling And Analysis

Experts at the Table, part 3: Juggling accuracy and fidelity while making the problem solvable with finite compute resources and exciting developme...

Power Modeling and Analysis

Experts at the Table, part 2: What does a power model look like and how do you ensure software utilizes power control properly?

More Roundtables »



Multimedia

Hybrid Memory

Tech Talk: How long can DRAM scalIng continue?

Huge Performance Gains Ahead

Where the next boosts will come from and why.

UPF-Aware Clock-Domain Crossing

How to minimize the impact of CDC on power at RTL.

Aging Effects

How to model circuit degradation at advanced nodes.

In-Design Power Rail Analysis

What can go wrong with power analysis at advanced nodes.

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

Editor's Note

Making AI Run Faster

Why inferencing is the next battleground.
October 11, 2018
Power Awareness

ML Becomes Useful For Variation Coverage

Engineering teams are starting to make SoC design choices based on manufactur...
Best Of Both: LP & HP

Re-using Common Simulation Set-Up Processes To Speed Regr...

A new reuse methodology shortens drawn-out design verification cycles.
IP And LP In SoCs

Overcoming Low Power Verification Challenges For Mixed-Si...

A low power methodology using a combination of static and dynamic verification.
Spotlight On Reliability

Functional Safety And Requirements Engineering

Using an integrated model-based flow for more efficient safety-aware design.
A Bit About Memory

ADAS Further Extends 7nm Challenges

Automotive chipmakers face requirements not found in other consumer electronics.
Everything Low Power

Processors Are Exciting Again

The move away from general-purpose CPUs is driving architectural innovation.
Electromagnetic Crosstalk

Electromagnetic Analysis and Signoff: Cost Savings

How to improve reliability, trim manufacturing costs, and shorten time to mar...
September 18, 2018
Let's Talk PVT Monitoring

5 Reasons Why In-Chip Monitoring Is Here To Stay

From identifying hot spots to individualizing optimization schemes, it's impo...
September 13, 2018
At The Core

Open Throttle On Automotive Innovation

Functional safety takes focus as the autonomous and semi-autonomous vehicle m...
Power Source

Getting Ahead With Early Power Analysis

Increased power density is causing mounting power and thermal concerns that n...
August 9, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

RISC-V: More Than a Core

Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.

Power Delivery Affecting Performance At 7nm

Slowdown due to impact on timing, and dependencies between power, thermal and timing that may not be caught by signoff tools.

RISC-V Inches Toward The Center

Access to source code makes it attractive for custom applications, but gaps remain in the tool flow and in software.

Machine Learning Shifts More Work to FPGAs, SoCs

SoC bandwidth, integration expand as data centers use more FPGAs for machine learning.

EUV Pellicle, Uptime And Resist Issues Continue

Problems won’t derail next-gen litho, but could limit use and affect schedules.