Agentic AI Is Changing Data Center Architectures
Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs, GPUs, and NPUs to eliminate memory bottlenecks, reduce lat...
Can AI Create Missing Models?
It depends on what those models are used, which also can have a big impact on the cost.
PCIe Benefits From AI, Despite Scaling Protocols
CXL is also gaining traction in AI processing, while MIPI and others are growing at the edge.
Chiplets Need A New Workflow
Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early an...
Flash Getting Stacked High-Bandwidth Version
Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.
Gates Add Functionality, But Wires Create Problems
Wires are treated as a lesser concern, but their neglect is becoming critical at advanced nodes.
Can Edge AI Keep Up?
As models evolve faster than silicon cycles, experts weigh how much adaptability architects can afford without sacrificing power, area, or efficiency.
DRAM’s Whac‑A‑Mole Security Crisis
New refresh commands chase Rowhammer and Rowpress, but a permanent fix remains years away.
A New Era For Co-Processing
Processor architectures are evolving faster than ever, but they still lag the pace of AI development. Chip architects must predict what will be req...
Fast Isn’t Fast Enough: Redefining Metrics for Edge AI
Why latency guarantees, memory movement, power budgets, and rapid model deployment now matter more than raw TOPS.
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Can Edge AI Keep Up?
As models evolve faster than silicon cycles, experts weigh how much adaptability architects can afford without sacrificing power, area, or efficiency.
Fast Isn’t Fast Enough: Redefining Metrics for Edge AI
Why latency guarantees, memory movement, power budgets, and rapid model deployment now matter more than raw TOPS.
Balancing Training, Quantization, And Hardware Integratio...
Evolving challenges and strategies in AI/ML model deployment and hardware optimization have a big impact on NPU architectures.
Addressing Critical Tradeoffs In NPU Design
Flexibility, future-proofing, and performance considerations for neural processing units.
How And Why To Optimize NPUs
PPA constraints need to be paired with real workloads, but they also need to be flexible to account for future changes.
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New USB Standards: Benefits And Incompatibilities
A roadmap for integrating different versions of the USB and eUSB.
1 Megawatt Racks In Data Centers
A look inside the next-generation AI server rack.
New CPU Memory Module
Benefits and questions surrounding a next-gen low-power standard for high-performance compute.
Why More CPUs Are Needed For Agentic AI
General-purpose processing demands will multiply once machines are talking to machines.
State Of The Market For Edge Silicon
What makes one AI chip better than another?
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