Low Power-High Performance

Top Stories

How Reliable Are FinFETs?

Chipmakers wrestle with EOS, ESD and other power-related issues as leading-edge chips are incorporated into industrial and automotive applications.

Using CNNs To Speed Up Systems

Just relying on faster processor clock speeds isn't sufficient for vision processing, and the idea is spreading to other markets.

Is Design Innovation Slowing?

The answer appears to be a resounding no, but innovation isn't necessarily happening in the same places as in the past.

IP Challenges Ahead

Part 2: For the IP industry to remain healthy it has to constantly innovate, but it's getting harder.

Dealing With System-Level Power

New tools, standards, languages and methodologies will be necessary to automate growing challenges at all process nodes.

IoT Myth Busting

How cost-sensitive are IoT edge devices, what are the real drivers for this industry, and what is the impact on EDA and IP?

Is The IP Industry Healthy?

First of two parts: IP has grown to become the largest segment of EDA revenue, but is it sustainable?

Modeling On-Chip Variation At 10/7nm

Timing and variability have long been missing from automated transistor-level simulation tools. At advanced nodes, an update will be required.

Transient Power Problems Rising

At 10/7nm, power management becomes much more difficult; old tricks don't work.

Safety Plus Security: A New Challenge

First in a series: There is a price to pay for adding safety and security into a product, but how do you assess that and control it? The implicatio...

More Top Stories »



Round Tables

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 3: Modeling accuracy, skin effects and new packaging techniques take center stage.

The Future Of Memory

Experts at the table, part 3: Security, process variation, shortage of other IP at advanced nodes, and too many foundry processes.

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 2: Heat is becoming a serious issue as thermal densities rise and this creates problems for industries such as automotiv...

Optimization Challenges For 10nm And 7nm

Experts at the Table, part 1: What will it take to optimize a design at 10nm and 7nm? The problem gets harder with each new node.

Mixed-signal/Low-power Design

Experts at the table, part 3: EDA vendors respond to the challenges posed by the chip companies.

More Roundtables »



Multimedia

Tech Talk: ADAS

What will change in automotive design on the road to autonomous vehicles.

Tech Talk: 7nm Power

Dealing with thermal effects, electromigration and other issues at the most advanced nodes.

Tech Talk: Neural Networks

How to design and implement convolution neural networks, and what to watch out for.

Tech Talk: Power Signoff

A look at the impact of margin in advanced designs and how to ensure there is sufficient coverage.

Tech Talk: Micro-Architecting Power

A deep dive into how to save power by leveraging idle time.

More Multimedia »



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Latest Blogs

Editor's Note

Rethinking Computing Fundamentals

Memory and processors are still separate, but that could change as the volume of...
Power Awareness

Computer Vision Powers Startups, Bleeding Edge Processes

It’s an exciting time to be involved in designing computer vision applications...
Everything Low Power

I Say 'High' [Performance], You Say 'Low' [Power]

Optimizing for the lowest power in a high-frequency, high-switching design....
A Bit About Memory

Enabling Higher System Performance With NVDIMM-N

Alternatives to traditional DRAM are needed to meet the bandwidth and latency de...
Best Of Both: LP & HP

UPF Power Domains And Boundaries

Understanding the fundamental parts of UPF constructions....
At The Core

System Design Considerations For Embedded Heterogeneous Multiprocessing (HMP)

Integrating functionally asymmetric compute elements requires unique system desi...
IP And LP In SoCs

Enabling UHD Or 4K Resolution Displays Using Data Stream Compression

Overcoming bandwidth limitations of MIPI DSI with visually lossless compression....
Power Source

Design For Silicon Success At 7nm

Rising complexity and tighter design margins increase the cost, and likelihood, ...
On-Chip Power Integrity

10nm And 7nm Routability - How Is Your CAD Flow Doing?

Power integrity optimization can no longer be a reactive step in the backend pro...
Power Architect

TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue

10nm heads into full swing, with 7nm and 5nm on the horizon....

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

How Reliable Are FinFETs?

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