Low Power-High Performance

Top Stories

Redefining The Power Delivery Network

Getting power around a complex package, which include externally sourced chiplets, may come with a higher cost than some are prepared to pay.

Preparing For A Barrage Of Physical Effects

A perfect storm of miniaturization at 3nm and advanced packaging is forcing design teams to confront issues they often ignored in the past.

Power And Performance Optimization At 7/5/3nm

Experts at the Table: What happens when AI chips max out at reticle size?

Smaller Nodes, Much Bigger Problems

Ansys' chief technologist digs into looming issues with device scaling, advanced packaging and AI everywhere.

Maximizing Value Post-Moore’s Law

The value of a semiconductor can be difficult to measure because it involves costs and benefits over time. As market segments feel different pressu...

Moving Data And Computing Closer Together

This is far from simple, but the power/performance and latency benefits are potentially huge.

Designing For Extreme Low Power

Power is becoming a differentiator in many designs, and for IoT and edge devices it may be the most important competitive differentiation.

Power Impact At The Physical Layer Causes Downstream Effects

PHYs have a growing impact on performance and power in both planar and multi-die designs.

What’s After PAM-4?

Second of two parts: Parallel vs. serial options

High-Speed Signaling Drill-Down

First of two parts: Different schemes emerge for moving signals down channels more quickly.

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Round Tables

Power And Performance Optimization At 7/5/3nm

Experts at the Table: What happens when AI chips max out at reticle size?

Addressing Pain Points In Chip Design

Partitioning, debug and first-pass working silicon lead the list of problems that need to be solved.

Why DRAM Won’t Go Away

New materials, new architectures and higher density have limited what can be done with DRAM, but it's still king (Experts At The Table Part 3)

DRAM Tradeoffs: Speed Vs. Energy

Experts at the Table: Which type of DRAM is best for different applications, and why performance and power can vary so much.

HBM2 Vs. GDDR6: Tradeoffs In DRAM

Experts at the Table, part 1: Choices vary depending upon application, cost and the need for capacity and bandwidth, but the number of options is c...

More Roundtables »


Ins And Outs Of In-Circuit Monitoring

Techniques to predict failures and improve reliability.

Visualizing Differences In Analog Design

Why analog engineers require visuals, why digital engineers do not.

High-Performance Memory For AI And HPC

Processing more data much more quickly.

Reliability In Automotive Chips

Understanding the mission profile and how that changes over time.

Where Timing And Voltage Intersect

Factors that limit whether a design can perform to spec.

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Latest Blogs

Editor's Note

The Next Leap

The race to increase performance by orders of magnitude.
August 14, 2020
IP And LP In SoCs

The Emergence Of Hardware As A Key Enabler For The Age Of...

The design-by-optimization paradigm calls for a new way of looking at how har...
August 13, 2020
Spotlight On Reliability

Mission Profiles In The Automotive Development Process

Standardization efforts are underway to ensure information can be accurately ...
Best Of Both: LP & HP

How UVM Callbacks Simplify Assertion Validation

Saving time by eliminating the need to code a new sequence for each scenario.
A Bit About Memory

Scaling AI/ML Training Performance With HBM2E Memory

Continued increases in memory capacity and bandwidth are needed to keep AI ac...
At The Core

Semiconductors And The Climate Curve

The impact of data analytics and AI on global energy use and what can be done...
Let's Talk PVT Monitoring

Managing Worst Case Power Conditions

Increased process variation and the end of Dennard scaling combine to mean th...
Everything Low Power

Make Acute Angles A Sharp Problem Of The Past

Automatically correcting sharp angles and acid traps with minimal change to r...
Power Source

Expanding Automotive Safety With SOTIF

Ensuring that components of a safety system not only work as designed but als...
The Disruptive Edge

Different Roles, Different Tools

On a big chip, tools to support communication are a critical factor in success.
July 9, 2020

Knowledge Centers
Entities, people and technologies explored

  Trending Articles

Manufacturing Bits: July 21

Intel’s next-gen MRAM; silicon oxide ReRAM; FeFETs.

RISC-V Gaining Traction

Experts at the Table: Extensible instruction-set architecture is drawing attention from across the industry and supply chain.

Universal Verification Methodology Running Out Of Steam

It’s time to move up in abstraction again as a complexity overwhelms a key approach.

The Race To Much More Advanced Packaging

Hybrid bonding opens up a big improvement in die-to-die performance, but getting there is not trivial.

Speeding Up The R&D Metrology Process

The goal is to use fab-like methods in the lab, but that’s not easy.