Low Power-High Performance

Top Stories

Defining Edge Memory Requirements

Edge compute covers a wide range of applications. Understanding bandwidth and capacity needs is critical.

IoT Wireless Battles Ahead

Tradeoffs include power, performance, security. Each standard has its own benefits and drawbacks.

Chip Dis-Integration

Continued integration is no longer the natural way forward for semiconductors. What needs to happen to make it easier?

Near-Threshold Issues Deepen

Process variation plus timing are adding to low-power challenges at the most advanced nodes.

Complexity, Reliability And Cost

Fraunhofer EAS's top scientist digs into new technical and business challenges shaping the semiconductor industry.

Ensuring Chip Reliability From The Inside

In-chip monitoring techniques are growing for automotive, industrial, and data center applications.

Analog Migration Equals Redesign

Advanced nodes are forcing design teams to make tradeoffs at each new node and with each new process.

Power Optimization Strategies Widen

Different markets are heading in different directions, raising questions about whether the chip industry can effectively respond to all of those de...

System-Level Power Modeling Takes Root

Why modeling power much earlier has suddenly become so critical for so many applications.

Does Power Verification Work?

Verification implies comparison against an expected result, but the industry has yet to define how this works for power. How are power bugs found?

More Top Stories »

Round Tables

Power Modeling And Analysis

Experts at the Table, part 3: Juggling accuracy and fidelity while making the problem solvable with finite compute resources and exciting developme...

Power Modeling and Analysis

Experts at the Table, part 2: What does a power model look like and how do you ensure software utilizes power control properly?

Power Modeling And Analysis

Experts at the Table, part 1: Are power models created early enough to be useful, and is that the best approach?

IP Challenges Ahead

Part 2: For the IP industry to remain healthy it has to constantly innovate, but it's getting harder.

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 3: Modeling accuracy, skin effects and new packaging techniques take center stage.

More Roundtables »


Tech Talk: Data-Driven Design

How more data is shifting memory architectures.

Tech Talk: HBM vs. GDDR6

A look at two different memory options, and the pros and cons of each.

Tech Talk: Shrink Vs. Package

Tradeoffs between putting everything onto a single chip and different advanced packaging options.

Tech Talk: Analog Simplified

Why it's so critical to speed up analog design across a broad swath of markets, and how to get there.

Tech Talk: Electrical Overstress

How to plan for electrical overstress and aging at advanced nodes and in safety-critical designs.

More Multimedia »

See All Posts in Low Power-High Performance »

Latest Blogs

IP And LP In SoCs

Enabling Ethernet Time-Sensitive Networking With Automoti...

Behind the standard that enables predictable latency and guaranteed bandwidth...
June 18, 2018
Best Of Both: LP & HP

Three Steps To Low Power Coverage Closure

Verifying the complex interactions between power elements at a high abstracti...
Everything Low Power

Can Machine Learning Chips Help Develop Better Tools With...

New AI chips require an extreme level of architectural complexity, making rou...
Editor's Note

Blazing-Fast Performance

A look inside the world's fastest computer, and why it now matters to many mo...
June 14, 2018
Electromagnetic Crosstalk

Is It Time To Take Inductance And Electromagnetic Effects...

Experts disagree about the impact of crosstalk on today's large mixed-signal ...
Power Source

Beyond Signoff

To deal with increased variability at advanced nodes, new methodologies are n...
Spotlight On Reliability

Upcoming System Modeling Challenges

Why it's important to incorporate reliability information into the concept ph...
Let's Talk PVT Monitoring

Process Detection & Variability

Designing for worst-case process variation can erode the gains made by migrat...
A Bit About Memory

5G Wireless Infrastructure Pushes High-Speed SerDes Proto...

Reducing SerDes latency variation and jitter is necessary for long-reach netw...
At The Core

Seven Steps To Build A Successful IoT Solution

Considering the hardware, software, and security choices available to IoT dev...
Power Awareness

Heterogeneous Hubbub

The combination of heterogenous architectures and RISC-V is encouraging new t...
March 8, 2018

Knowledge Centers
Entities, people and technologies explored

  Trending Articles

FPGAs Becoming More SoC-Like

Lines blur as processors are added into traditional FPGAs, and programmability is added into ASICs.

Big Trouble At 3nm

Costs of developing a complex chip could run as high as $1.5B, while power/performance benefits are likely to decrease.

Machine Learning’s Limits

Experts at the Table, part 1: Why machine learning works in some cases and not in others.

Chip Dis-Integration

Continued integration is no longer the natural way forward for semiconductors. What needs to happen to make it easier?

IBM Takes AI In Different Directions

What AI and deep learning are good for, what they’re not good for, and why accuracy sometimes works against these systems.