Low Power-High Performance

Top Stories

What Makes A Chip Design Successful Today?

Maximum flexibility is no longer the reliable path to product success. While flexibility must be there for a purpose, it also can be a liability.

Impacts Of Reliability On Power And Performance

Determinism and coherency are becoming increasingly important as chips are used across a wide range of applications.

How To Improve Analog Design Reuse

Existing design approaches remain inefficient, error-prone and highly customized, but that could change.

Design For Advanced Packaging

Stacking die is garnering more attention, but design flows aren’t fully ready to support it.

Taming NBTI To Improve Device Reliability

Negative-bias temperature instability can cause an array of problems at advanced nodes and reduced voltages.

Computing Way Outside Of A Box

Arm's CTO talks about how AI and the end of Moore's Law are shaking up processor design.

The Building Blocks Of Future Compute

How Arm sees its role in emerging segments of tomorrow’s compute challenges.

RISC-V: More Than a Core

Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.

Power Issues Grow For Cloud Chips

Optimizing processor design in high-performance computing now requires lots of small changes.

Reliability, Machine Learning And Advanced Packaging

Experts at the Table, part 1: The biggest concerns in chip design and how new markets and technologies are affecting them.

More Top Stories »



Round Tables

Aging In Advanced Nodes

Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.

Process Variation Not A Solved Issue

Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.

Architecting For AI

Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?

Power Modeling And Analysis

Experts at the Table, part 3: Juggling accuracy and fidelity while making the problem solvable with finite compute resources and exciting developme...

Power Modeling and Analysis

Experts at the Table, part 2: What does a power model look like and how do you ensure software utilizes power control properly?

More Roundtables »



Multimedia

Making Sense Of DRAM

What kind of memory is used where and why.

Hybrid Memory

Tech Talk: How long can DRAM scalIng continue?

Huge Performance Gains Ahead

Where the next boosts will come from and why.

UPF-Aware Clock-Domain Crossing

How to minimize the impact of CDC on power at RTL.

Aging Effects

How to model circuit degradation at advanced nodes.

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

At The Core

How to nail functional safety in your next design

Lock step, redundant execution and split-lock—which is better and why.
December 14, 2018
Editor's Note

Security, Scaling and Power

Why these three things are related and what it means for Intel and the rest o...
December 13, 2018
IP And LP In SoCs

Efficient Low Power Verification & Debug Methodology...

Making sure subtle bugs do not escape in low power designs.
Best Of Both: LP & HP

A New Approach To Resistance Extraction For Unconventiona...

How 2D fracturing can provide accurate results in a timely manner.
A Bit About Memory

Taking Steps Toward Hybrid Memory

Intelligently utilizing multiple types of memory in a single subsystem.
Power Awareness

Aging Analysis Hits Mainstream

Increasingly, the ability to address transistor aging is showing up in EDA to...
November 8, 2018
Spotlight On Reliability

Interaction Of Hard IP And Chip-Package

Conflicting goals make arranging copper pillars or micro bumps around hard IP...
Everything Low Power

Psst, Says 5G… Wanna See What My New Antenna Tech C...

Power consumption remains a major barrier to 5G rollout.
Electromagnetic Crosstalk

Electromagnetic Analysis and Signoff: Cost Savings

How to improve reliability, trim manufacturing costs, and shorten time to mar...
September 18, 2018
Let's Talk PVT Monitoring

5 Reasons Why In-Chip Monitoring Is Here To Stay

From identifying hot spots to individualizing optimization schemes, it's impo...
September 13, 2018
Power Source

Getting Ahead With Early Power Analysis

Increased power density is causing mounting power and thermal concerns that n...
August 9, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

AI Chip Architectures Race To The Edge

Companies battle it out to get artificial intelligence to the edge using various chip architectures as their weapons of choice.

Foundries Prepare For Battle At 22nm

Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiation. But where will chipmakers go after 28nm?

Where Advanced Packaging Makes Sense

Experts at the Table, Part 1: Impact on the supply chain, who’s using advanced packaging, and the cost of packaging versus device scaling.

Getting Down To Business On Chiplets

Consortiums seek ways to ensure interoperability of hardened IP as way of cutting costs, time-to-market, but it’s not going to be easy.

Looking Beyond The CPU

While CPUs continue to evolve, performance is no longer limited to a single processor type or process geometry.