Low Power-High Performance

Top Stories

Designs Beyond The Reticle Limit

Chips are hitting technical and economic obstacles, but that is barely slowing the rate of advancement in design size and complexity.

Dealing With Sub-Threshold Variation

The value and challenges of circuits being not quite on or off.

Difficult Memory Choices In AI Systems

Tradeoffs revolve around power, performance, area, and bandwidth.

Performance and Power Tradeoffs At 7/5nm

Experts at the Table: Security, reliability, and margin are all in play at leading-edge nodes and in advanced packages.

Increase In Analog Problems

New data suggests that more chips are being forced to respin due to analog issues.

Slower Metal Bogs Down SoC Performance

Interconnects are becoming the limiter at advanced nodes.

Searching For Power Bugs

To find wasted power means you understand what to expect, how to measure it, and how it correlates to real silicon. We are further from that than y...

Confusion Grows Over Packaging And Scaling

The number of options is increasing, but tooling and methodologies haven't caught up.

Startup Funding: September 2020

Big investment in EV, batteries, and data center chips as 26 companies raise $2.6B.

Custom Designs, Custom Problems

Experts at the Table: Power and performance issues at the most advanced nodes.

More Top Stories »



Round Tables

Performance and Power Tradeoffs At 7/5nm

Experts at the Table: Security, reliability, and margin are all in play at leading-edge nodes and in advanced packages.

Custom Designs, Custom Problems

Experts at the Table: Power and performance issues at the most advanced nodes.

Power And Performance Optimization At 7/5/3nm

Experts at the Table: What happens when AI chips max out at reticle size?

Addressing Pain Points In Chip Design

Partitioning, debug and first-pass working silicon lead the list of problems that need to be solved.

Why DRAM Won’t Go Away

New materials, new architectures and higher density have limited what can be done with DRAM, but it's still king (Experts At The Table Part 3)

More Roundtables »



Multimedia

112G SerDes Reliability

How to ensure consistent performance in the real world.

Ins And Outs Of In-Circuit Monitoring

Techniques to predict failures and improve reliability.

Visualizing Differences In Analog Design

Why analog engineers require visuals, why digital engineers do not.

High-Performance Memory For AI And HPC

Processing more data much more quickly.

Reliability In Automotive Chips

Understanding the mission profile and how that changes over time.

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

Power Source

Elasticity Without Compromise

Compute power to infinity and beyond.
November 25, 2020
Editor's Note

The Next Phase Of Computing

Apple's new chip is just the tip of a technological revolution.
November 16, 2020
Spotlight On Reliability

Electronics For Quantum Communications

Moving from classic encryption algorithms with increasing key lengths to comm...
November 12, 2020
Best Of Both: LP & HP

Customizing Low-Power Platforms Using UPF Dynamic Properties

A methodology for building low-power verification platforms using UPF informa...
At The Core

Building Billions Of Batteryless Devices

The greatest challenge the Internet of Things faces is how those 'things' wil...
A Bit About Memory

The Expanding Universe Of MIPI Applications

Why this interface is no longer just about mobile phones.
Everything Low Power

Arm Goes For Performance

Recently announced high-end processors are pushing performance capabilities t...
IP And LP In SoCs

The Challenge Of Balancing Performance And Accuracy For A...

Process variability, physical effects, and the impact of interconnect are cri...
November 10, 2020
Let's Talk PVT Monitoring

Sensors Will Proliferate In SoCs

As geometries shrink, the ability to monitor what's going on in a device is i...
October 15, 2020
The Disruptive Edge

Different Roles, Different Tools

On a big chip, tools to support communication are a critical factor in success.
July 9, 2020

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Uniquely Identifying PCBs, Subassemblies, And Packaging

New approaches to preventing counterfeiting across the supply chain.

EUV Challenges And Unknowns At 3nm and Below

Rising costs, complexity, and fuzzy delivery schedules are casting a cloud over next-gen lithography.

Dealing With Security Holes In Chips

Challenges range from constant security updates to expected lifetimes that last beyond the companies that made them.

Challenges Linger For EUV

Experts at the Table: The challenges of putting EUV into production, and why DRAM will require advanced litho in the future.

Growing Complexity Adds To Auto IC Safety Challenges

Building together a verification approach for safety and security in automotive chips is complex, multi-faceted, and extremely difficult.