Low Power-High Performance

Top Stories

Designing For The Edge

Growth in data is fueling many more options, but so far it's not clear which of them will win.

Target: 50% Reduction In Memory Power

Is it possible to reduce the power consumed by memory by 50%? Yes, but it requires work in the memory and at the architecture level.

Low Power Meets Variability At 7/5nm

Reductions in voltage, margin and increases in physical effects are making timing closure and signoff much more difficult.

Optimization Challenges For Safety And Security

The road to optimized tradeoff automation is long. Changing attributes along the way can make it even more difficult.

The Growing Challenge Of Thermal Guard-Banding

Margin is still necessary, but it needs to be applied more precisely than in the past.

Using Less Power At The Same Node

When going to a smaller node is no longer an option, how do you get better power performance? Several techniques are possible.

Memory Tradeoffs Intensify in AI, Automotive Applications

Why choosing memories and architecting them into systems is becoming much more difficult.

Using Analog For AI

Can mixed-signal architectures boost artificial intelligence performance using less power?

Gearing Up For 5G

This new communications standard could transform architectural decisions across the industry, but not right away and not necessarily in obvious ways.

Adapting Mobile To A Post-Moore’s Law Era

New techniques, architectures and approaches are making up for a reduction in scaling benefits.

More Top Stories »

Round Tables

Planning For 5G And The Edge

Experts at the Table, part 2: Understanding 5G's benefits, limitations and design challenges.

Process Variation And Aging

Experts at the Table, part 2: How the very fast progress of the semiconductor industry is making transistor aging even more difficult.

Aging In Advanced Nodes

Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.

Process Variation Not A Solved Issue

Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.

Architecting For AI

Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?

More Roundtables »


Multi-Physics At 5/3nm

Why process, voltage and temperature are so interrelated at future nodes, and what impact that has on design.

GDDR6 – HBM2 Tradeoffs

What type of DRAM works best where.

2.5D, 3D Power Integrity

Things to consider in advanced packaging.

Boosting Analog Reliability

Dealing with variability and physical effects in mixed signal designs.

Thermal Guard-Banding

Why more precision is necessary at advanced nodes.

More Multimedia »

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Latest Blogs

Editor's Note

More Memory And Processor Tradeoffs

Why power, performance and area are becoming increasingly difficult to balance.
April 11, 2019
Best Of Both: LP & HP

The Weather Report: 2018 Study On IC/ASIC Verification Tr...

Increased design size is only one dimension of the growing complexity challenge.
A Bit About Memory

GDDR6 And HBM2: Signal Integrity Challenges For AI

Why memory choices for AI systems depend on the application.
IP And LP In SoCs

Exascale Emulation Debug Challenges

Length of tests, failure reproduction, and the sheer amount of data generated...
At The Core

Taking Security-By-Design To The Next Level

Trusted, independent security testing is critical to enabling widespread depl...
Everything Low Power

IC Test: Doing It At The Right Place At The Right Time

Understand the different DFT technologies to know when to insert them into a ...
March 14, 2019
Let's Talk PVT Monitoring

How To Reduce Thermal Guard-Banding

What a difference a few degrees can make.
February 14, 2019
Electromagnetic Crosstalk

How to Make Sure IP will Float in the Rough SoC Sea

The impact of coupling on designs and what to watch out for.
December 19, 2018
Power Awareness

Aging Analysis Hits Mainstream

Increasingly, the ability to address transistor aging is showing up in EDA to...
November 8, 2018
Spotlight On Reliability

Interaction Of Hard IP And Chip-Package

Conflicting goals make arranging copper pillars or micro bumps around hard IP...
Power Source

Getting Ahead With Early Power Analysis

Increased power density is causing mounting power and thermal concerns that n...
August 9, 2018

Knowledge Centers
Entities, people and technologies explored

  Trending Articles

Making Chip Packaging Simpler

The promise of advanced packaging is being able to integrate heterogeneous chips, but a lot of work is needed to make that happen.

EUV Arrives, But More Issues Ahead

Improvement still needed for uptime, defectivity, line edge roughness and process flows.

Single Vs. Multi-Patterning EUV

Why this choice isn’t as obvious as it might look.

The 7nm Pileup

Why are so many companies rushing to do 7nm designs?

3D NAND Metrology Challenges Growing

Rising costs and gaps in equipment emerge as technology scales; new tools under development.