Low Power-High Performance

Top Stories

Wrestling With Variation In Advanced Node Designs

Margin is no longer effective, so now the problem has to be solved on the design side.

Reducing Power At RTL

Dependencies, different methodologies, and a growing number of variables make this an increasingly challenging and complex problem.

Brighter Future For Photonics

Will progress in 3D stacking translate into increased opportunities for photonics chips? Progress still has to be made in several areas.

Non-Volatile Memory Tradeoffs Intensify

Why NVM is becoming so application-specific and what the different options are.

Analog: Avoid Or Embrace?

Data converters are required whenever you move between the analog and digital domains, and they present both challenges and opportunities.

Priorities Shift In IC Design

AI, edge applications are driving design teams to find new ways to achieve the best performance per watt.

Moore’s Law, Supply Chains And Security

Big changes ahead, from design to deployment.

Managing Power Dynamically

Dynamic voltage and frequency scaling resurfaces, but it's not the only option to improve performance and lower power.

Interdependencies Complicate IC Power Grid Design

A number of technical challenges have come together to make power grid design one of the most challenging design issues today.

A New Dawn For IP

The IP industry, barely 20 years old, has been under constant change and evolution. The latest change requires vendors to become knowledge partners.

More Top Stories »



Round Tables

Addressing Pain Points In Chip Design

Partitioning, debug and first-pass working silicon lead the list of problems that need to be solved.

Why DRAM Won’t Go Away

New materials, new architectures and higher density have limited what can be done with DRAM, but it's still king (Experts At The Table Part 3)

DRAM Tradeoffs: Speed Vs. Energy

Experts at the Table: Which type of DRAM is best for different applications, and why performance and power can vary so much.

HBM2 Vs. GDDR6: Tradeoffs In DRAM

Experts at the Table, part 1: Choices vary depending upon application, cost and the need for capacity and bandwidth, but the number of options is c...

Planning For 5G And The Edge

Experts at the Table, part 2: Understanding 5G's benefits, limitations and design challenges.

More Roundtables »



Multimedia

Reliability In Automotive Chips

Understanding the mission profile and how that changes over time.

Where Timing And Voltage Intersect

Factors that limit whether a design can perform to spec.

Thermal Guardbanding

How more accurate measurements can impact efficiency and performance.

How Chips Age

Are current methodologies sufficient for ensuring that chips will function as expected throughout their expected lifetimes?

Bridging Math And Engineering In ML

How to combine two very different disciplines to create inferencing chips.

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

Editor's Note

Thinking About AI Power In Parallel

Next steps in adding efficiency into complex systems.
February 13, 2020
Spotlight On Reliability

Artificial Intelligence For Industrial Applications

Perspectives for the integration of hardware and algorithms.
A Bit About Memory

Enabling Integration Success Using High-Speed SerDes IP

How an IP vendor can help integrate SerDes IP in an ASIC design project and s...
IP And LP In SoCs

How AI In Edge Computing Drives 5G And The IoT

Understanding what edge computing really is and how it fits in pervasive comp...
Best Of Both: LP & HP

Earlier Is Better In Latch-Up Detection

Performing topological analysis on the schematic netlist quickly identifies l...
Everything Low Power

Moore And More

Chiplets, packaging and some interesting new challenges.
Let's Talk PVT Monitoring

The Future Of Embedded Monitoring, Part 1

Chip designers need more data to hear what chips are saying in real time.
At The Core

AI: A Perfect Solution But At What Cost?

Cloud AI won’t cope with the coming device data deluge on its own. And that...
Power Source

Using Digital Image Correlation To Determine BGA Warpage

An important technique for capturing an electronic component’s response to ...
January 16, 2020
The Disruptive Edge

SAR ADCs For Machine-To-Machine Connections

ADC architecture considerations for applications requiring fast sampling rates.
Power Awareness

Aging Analysis Hits Mainstream

Increasingly, the ability to address transistor aging is showing up in EDA to...
November 8, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

The MCU Dilemma

Microcontroller vendors are breaking out of the box that has constrained them for years. Will new memory types and RISC-V enable the next round of changes?

Moving To GAA FETs

Why finFETs are running out of steam, and what happens next.

Week In Review: Design, Low Power

Semi M&A strong in 2019; Qorvo buys Decawave; Presto buys Delta.

Chips, Business And The Coronavirus

Broad implications for a global supply chain.

How AI In Edge Computing Drives 5G And The IoT

Understanding what edge computing really is and how it fits in pervasive computing.