Low Power-High Performance

Top Stories

AI Architectures Must Change

Using the Von Neumann architecture for artificial intelligence applications is inefficient. What will replace it?

Chip Aging Becomes Design Problem

Assessing the reliability of a device requires adding more physical factors into the analysis, many of which are interconnected in complex ways.

More Processing Everywhere

Arm's CEO contends that a rise in data will fuel massive growth opportunities around AI and IoT, but there are significant challenges in making it ...

Process Variation Not A Solved Issue

Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.

On-Chip Monitoring Of FinFETs

Moortec's CEO focuses on simulation's limits at advanced nodes and why a more granular approach is necessary to improve reliability and lower power...

Data Center Power Poised To Rise

Shift to cloud model has kept power consumption in check, but that benefit may have run its course.

5nm Design Progress

Improvements in power, performance and area are much more difficult to achieve, but solutions are coming into focus.

Architecting For AI

Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?

Five DAC Keynotes

Thought-provoking talks about the future of technology, how to improve it, and what it means for design engineers.

Defining Edge Memory Requirements

Edge compute covers a wide range of applications. Understanding bandwidth and capacity needs is critical.

More Top Stories »



Round Tables

Process Variation Not A Solved Issue

Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.

Architecting For AI

Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?

Power Modeling And Analysis

Experts at the Table, part 3: Juggling accuracy and fidelity while making the problem solvable with finite compute resources and exciting developme...

Power Modeling and Analysis

Experts at the Table, part 2: What does a power model look like and how do you ensure software utilizes power control properly?

Power Modeling And Analysis

Experts at the Table, part 1: Are power models created early enough to be useful, and is that the best approach?

More Roundtables »



Multimedia

Aging Effects

How to model circuit degradation at advanced nodes.

In-Design Power Rail Analysis

What can go wrong with power analysis at advanced nodes.

Tech Talk: Data-Driven Design

How more data is shifting memory architectures.

Tech Talk: HBM vs. GDDR6

A look at two different memory options, and the pros and cons of each.

Tech Talk: Shrink Vs. Package

Tradeoffs between putting everything onto a single chip and different advanced packaging options.

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

Editor's Note

More Performance At The Edge

Scaling is about to take on a whole different look, and it not just from shri...
August 9, 2018
Everything Low Power

Power Reduction In A Constrained World

Why it's critical to make power a key vector for design convergence.
A Bit About Memory

High-Performance Memory At Low Cost Per Bit

Emerging applications drive the need for high memory capacity.
Power Source

Getting Ahead With Early Power Analysis

Increased power density is causing mounting power and thermal concerns that n...
IP And LP In SoCs

Impact Of IP On AI SoCs

Deep learning applications will call for specialized IP in the form of new pr...
Electromagnetic Crosstalk

Minimizing The Risk Of Electromagnetic Crosstalk Failures

Sensitivity to electromagnetic coupling is increasing. How can designers dete...
Spotlight On Reliability

Predictive Maintenance In Tomorrow’s Industries

Combining data analytics and process knowledge to predict machine failures in...
Best Of Both: LP & HP

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Em...

The fully-updated, and free, how-to guide for UVM is now available.
At The Core

Pace Quickens As Machine Learning Moves To The Edge

More powerful edge devices means everyday AI applications, like social robots...
Let's Talk PVT Monitoring

Explaining Adaptive Voltage Scaling And Dynamic Voltage F...

Voltage monitoring enables two techniques for optimizing in-chip conditions.
July 17, 2018
Power Awareness

Heterogeneous Hubbub

The combination of heterogenous architectures and RISC-V is encouraging new t...
March 8, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

The Chiplet Race Begins

DARPA and a number of major vendors are backing this modular approach, but hurdles remain.

AI Architectures Must Change

Using the Von Neumann architecture for artificial intelligence applications is inefficient. What will replace it?

Fabs Meet Machine Learning

D2S’ CEO sounds off on the impact of deep learning, EUV and other manufacturing advancements.

Artificial Intelligence Chips: Past, Present and Future

It’s been an uneven path leading to the current state of AI, and there’s still a lot of work ahead.

Data Center Power Poised To Rise

Shift to cloud model has kept power consumption in check, but that benefit may have run its course.