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Low Power-High Performance

Top Stories

Always-On, Ultra-Low-Power Design Gains Traction
Powering down most of a system is good for conserving batteries, but leaving some circuits on adds some complex challenges for design teams.
Published on April 14th,  2022 by Ann Steffora Mutschler

Architecting Faster Computers
Moving forward will require a fundamental reconsideration of logic.
Published on April 14th,  2022 by Brian Bailey

Increasing Performance With Data Acceleration
In-line acceleration boosts performance for radio access networks.
Published on April 14th,  2022 by Martha DeGrasse

Clocks Getting Skewed Up
The clock network is complex, critical to performance, but often it's treated as an afterthought. Getting this wrong can ruin your chip.
Published on March 30th,  2022 by Brian Bailey

Improving Memory Efficiency And Performance
CXL and OMI will facilitate memory sharing and pooling, but how well and where they work best remains debatable.
Published on March 28th,  2022 by Bryon Moyer

CXL and OMI: Competing or Complementary?
It depends on whom you ask, but there are advantages to both.
Published on March 23rd,  2022 by Bryon Moyer

Power Now First-Order Concern In More Markets
No longer a separate set of requirements, designers are prioritizing both power and performance in markets where performance has been the main goal.
Published on March 10th,  2022 by Ann Steffora Mutschler

Why Comparing Processors Is So Difficult
Some designs focus on power, while others focus on sustainable performance, cost, or flexibility. But choosing the best option for an application b...
Published on March 10th,  2022 by Brian Bailey

Robots Become More Useful In Factories
Automation includes increasing number and variety of bots as chips become more capable; cost of entry drops.
Published on March 10th,  2022 by John Koon

Improving PPA In Complex Designs With AI
Research shows significant improvement in time to market and optimization of key metrics.
Published on February 14th,  2022 by John Koon

More Top Stories »



Round Tables

Performance and Power Tradeoffs At 7/5nm
Experts at the Table: Security, reliability, and margin are all in play at leading-edge nodes and in advanced packages.
Published on October 27th,  2020 by Ed Sperling

Custom Designs, Custom Problems
Experts at the Table: Power and performance issues at the most advanced nodes.
Published on September 16th,  2020 by Ed Sperling

Power And Performance Optimization At 7/5/3nm
Experts at the Table: What happens when AI chips max out at reticle size?
Published on August 13th,  2020 by Ed Sperling

Addressing Pain Points In Chip Design
Partitioning, debug and first-pass working silicon lead the list of problems that need to be solved.
Published on November 13th,  2019 by Ed Sperling

Why DRAM Won’t Go Away
New materials, new architectures and higher density have limited what can be done with DRAM, but it's still king (Experts At The Table Part 3)
Published on September 18th,  2019 by Ed Sperling

More Roundtables »



Multimedia

The Ethernet Evolution
Why this technology has continue to thrive in data centers.
Published on March 1st,  2022 by Ed Sperling

Always-On DSPs
The best ways to deploy digital signal processors and why multiple DSPs are better than one.
Published on December 28th,  2021 by Ed Sperling

Low-Power Always-On Circuits
What happens when things never shut down?
Published on September 27th,  2021 by Ed Sperling

Problems In The Power Grid
How the electrification of everything will affect power generation, storage and availability.
Published on June 22nd,  2021 by Ed Sperling

Improving Power & Performance Beyond Scaling
How to reduce total cost of ownership in data centers.
Published on June 16th,  2021 by Ed Sperling

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

Spotlight On Reliability

How Do I Come To Trust An Electronic Component?
Determining what makes a dependable system.
April 14, 2022
by Roland Jancke
A Bit About Memory

High-Performance SerDes Enable The 5G Wireless Edge
The importance of a high-speed, low-latency cellular network for AI-powered I...
by Frank Ferro
At The Core

The Set Top Box Is Getting A Retrofit
New services that could be enabled through the processing power of digital TV...
by Pablo Fraile
IP And LP In SoCs

If These Chips Could Talk: Actionable Insights From Path ...
Getting feedback during chip bring up, production test, and deployment within...
by Ash Patel
Best Of Both: LP & HP

Reliable DRC Voltage Text Annotation Means Faster And Mor...
What is voltage text annotation and why do you need it in your IC design?
by Abdellah Bakhali
Design Reuse Made Real

Design-Aware Data Management For Hybrid Cloud
Working from home has become a standard operating practice for the semiconduc...
by Amit Varde
Everything Low Power

The Era Of Fluid Simulations In Hollywood
The rise of a new way to create blockbuster visual effects.
by Veena Parthan
Power Source

Driving Toward A Sustainable Future
How BMW uses physics-based analysis to assess the reliability of automotive e...
by Mary Kate Joyce
Linking Real And Digital Worlds

PCB Layout Tips For Low Side Gate Drivers With OCP
Avoid common noise coupling issues in layouts for high-current, fast-switchin...
March 10, 2022
by Weidong Chu
MIPI And Beyond

Innovation In C-PHY
How the physical layer specification achieves higher data rates at low transi...
May 18, 2021
by Ashraf Takla
Editor's Note

The Next Phase Of Computing
Apple's new chip is just the tip of a technological revolution.
November 16, 2020
by Ed Sperling

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Extending Copper Interconnects To 2nm

From low resistance vias to buried power rails, it takes multiple strategies to usher in 2nm chips.

by Laura Peters

Highly Selective Etch Rolls Out For Next-Gen Chips

Manufacturing 3D structures will require atomic-level control of what’s removed and what stays on a wafer.

by Mark LaPedus

Chiplets Enter The Supercomputer Race

Nations compete on speed using very different compute architectures.

by Mark LaPedus

Strategies For Faster Yield Ramps On 5nm Chips

Smart software finds more EUV stochastic defects and missing vias, improving wafer yield.

by Laura Peters

CXL and OMI: Competing or Complementary?

It depends on whom you ask, but there are advantages to both.

by Bryon Moyer

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