Low Power-High Performance

Top Stories

Circuit Aging Becoming A Critical Consideration

As reliability demands soar in automotive and other safety-related markets, tools vendors are focusing on an area often ignored in the past.

Waiting For Chiplet Interfaces

Plug-and-play approaches are gaining mindshare, even if some of the key pieces are missing.

HBM2 Vs. GDDR6: Tradeoffs In DRAM

Experts at the Table, part 1: Choices vary depending upon application, cost and the need for capacity and bandwidth, but the number of options is c...

In-Chip Monitoring Becoming Essential Below 10nm

Complex interactions and power-related effects require understanding of how chips behave in context of real-world use cases.

Chiplet Momentum Builds, Despite Tradeoffs

Pre-characterized tiles can move Moore's Law forward, but it's not as easy as it looks.

The Growing Uncertainty Of Sign-Off At 7/5nm

Checking the electrical characteristics of circuits is becoming much more challenging.

The Limits Of Energy Harvesting

Why the promise of unlimited power in end devices has achieved only spotty success.

Raising The Abstraction Level For Power

Finding the right abstraction for power analysis and optimization comes from tool integration.

Designing For The Edge

Growth in data is fueling many more options, but so far it's not clear which of them will win.

Target: 50% Reduction In Memory Power

Is it possible to reduce the power consumed by memory by 50%? Yes, but it requires work in the memory and at the architecture level.

More Top Stories »



Round Tables

HBM2 Vs. GDDR6: Tradeoffs In DRAM

Experts at the Table, part 1: Choices vary depending upon application, cost and the need for capacity and bandwidth, but the number of options is c...

Planning For 5G And The Edge

Experts at the Table, part 2: Understanding 5G's benefits, limitations and design challenges.

Process Variation And Aging

Experts at the Table, part 2: How the very fast progress of the semiconductor industry is making transistor aging even more difficult.

Aging In Advanced Nodes

Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.

Process Variation Not A Solved Issue

Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.

More Roundtables »



Multimedia

Memory Options And Tradeoffs

What kinds of memories work best where and why.

Latency Under Load: HBM2 vs. GDDR6

Why choosing memory depends upon data traffic.

New Challenges For Data Centers

Scalability and cost emerge as top issues with increased data volume.

Multi-Physics At 5/3nm

Why process, voltage and temperature are so interrelated at future nodes, and what impact that has on design.

GDDR6 – HBM2 Tradeoffs

What type of DRAM works best where.

More Multimedia »



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Latest Blogs

Editor's Note

Playing Into China’s Hands

A trade war couldn't occur at a worse time for the rest of the tech industry.
June 13, 2019
IP And LP In SoCs

Building Your First Chip For Artificial Intelligence? Rea...

To make more effective and optimized AI SoCs, look beyond traditional design ...
A Bit About Memory

HBM2e Offers Solid Path For AI Accelerators

AI processor performance is rapidly growing, making memory architecture choic...
Best Of Both: LP & HP

Speed Up P2P Resistance Debugging With Selective Highligh...

Use filters to remove layout data that is unused and unnecessary to speed ide...
The Disruptive Edge

Resetting Serial Memory When A System Failure Occurs

Serial flash devices that support JESD252 can overcome challenges associated ...
At The Core

Deep Learning Models With MATLAB And Cortex-A

An end-to-end workflow for deploying embedded machine learning.
Everything Low Power

IC Test: Doing It At The Right Place At The Right Time

Understand the different DFT technologies to know when to insert them into a ...
March 14, 2019
Let's Talk PVT Monitoring

How To Reduce Thermal Guard-Banding

What a difference a few degrees can make.
February 14, 2019
Electromagnetic Crosstalk

How to Make Sure IP will Float in the Rough SoC Sea

The impact of coupling on designs and what to watch out for.
December 19, 2018
Power Awareness

Aging Analysis Hits Mainstream

Increasingly, the ability to address transistor aging is showing up in EDA to...
November 8, 2018
Spotlight On Reliability

Interaction Of Hard IP And Chip-Package

Conflicting goals make arranging copper pillars or micro bumps around hard IP...

Knowledge Centers
Entities, people and technologies explored


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