Packaging, Test & Electronic Systems

Top Stories

Improving Yield, Reliability With Data

Outlier detection gaining attention as way of improving test and manufacturing methodologies.

Toward System-Level Test

What's working in test, what isn't, and where the holes are.

Integrated Passives Market Gets Active

IPDs take the place of discretes for mobile, IoT, wearables, and are gaining traction in advanced packaging.

Advanced Packaging’s Progress

STATS ChipPAC's CTO zeroes on different types of packages and what the pros and cons are for each.

Plugging Gaps In Advanced Packaging

Design-packaging-board flow getting more attention as multi-chip solutions proliferate.

Light In A Package

Why silicon photonics is so difficult, and why it's becoming more popular.

Get Ready For In-Mold Electronics

Changes in packaging under development for new applications and price points.

Inside Panel-Level Fan-Out Technology

Fraunhofer's panel experts dig into why this approach is needed and where the challenges are to making it work.

The Rising Value Of Data

Race begins to figure out what else can be done with data. But not all data is useful, and some of it is faulty.

Cheaper Fan-Outs Ahead

Demand for lower cost drives R&D for panel-level packaging. But which size?

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Round Tables

2.5D Surprises And Alternatives

First of two parts: Cost and supply chain issues remain as advanced packaging begins to ramp.

Stacked Die Changes

Experts at the table, part 3: How mature are high-speed interconnects and what hurdles remain for widespread adoption.

Stacked Die Changes

Experts at the table, part 2: Different coefficients of thermal expansion cause warpage problems; known good die issues.

Stacked Die Changes

Experts at the table, part 1: There are new and better options for packaging chips together as the semiconductor industry begins to figure out what...

More Roundtables »


Tech Talk: System In Package

Why advanced packaging is so important for autonomous driving and the semiconductor industry.

Tech Talk: 2.5D Issues

How ready is this packaging approach and what problems remain?

Tech Talk: 14nm And Stacked Die

Why the 14nm node will be long lived, and how it will be used in 2.5D and 3D-IC packages.

Tech Talk: 2.5D Stacked Die

What's the real motivation behind stacking die?

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Latest Blogs

Editor's Note

The Chiplet Option

More companies are assessing pre-built and pre-verified circuits as a way of red...
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The 2017 International Test Conference

The 48th annual gathering will look at the latest in test technology....
Inside Big Data

Is It Safe To Assume That All "Passed" Die Are Actually "Good" Die?

Detecting tricky test escapes and preventing defective parts from getting into y...
The Human Machine Interface

The Future Of Human/Machine Interaction Is Personal

The implications of technology in an age of pervasive accessibility....
Accelerating Design & Test

Tips For Research Grants

How to write a successful proposal that incorporates a transition to practice pl...
EDA For Manufacturability

Crossing The Chasm: Uniting SoC And Package Verification

EDA companies, OSATs, and foundries must collaborate to ensure wafer-level packa...

Knowledge Centers
Entities, people and technologies explored

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Unsolved Litho Issues At 7nm

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