Packaging, Test & Materials

Top Stories

Choosing The Right Interconnect
Packaging options increasing as chipmakers vie for higher performance, lower power and faster time to market.
Published on April 9th,  2018 by Ed Sperling

Embedded Die Packaging Emerges
Why this technology approach is suddenly getting attention, and what hurdles still remain.
Published on April 9th,  2018 by Mark LaPedus

Wireless Test Faces New Challenges
The advent of 5G and other emerging wireless technologies make test more difficult. Over-the-air testing is one possible solution.
Published on April 9th,  2018 by Jeff Dorsch

Toward High-End Fan-Outs
Denser interconnects, stacked die could rival 2.5D approaches.
Published on March 5th,  2018 by Ed Sperling

Finding Faulty Auto Chips
The road to zero defects requires some new tactics.
Published on March 5th,  2018 by Mark LaPedus

Looking At Test Differently
How test strategies are changing to adapt to smaller batches of more complex designs and new packaging technologies.
Published on March 5th,  2018 by Ed Sperling

Fan-Out Wars Begin
The number of low-density packaging options is increasing as the popularity of advanced packaging grows.
Published on February 5th,  2018 by Mark LaPedus

Cheaper Packaging Options Ahead
Low-cost alternatives to interposers could have a big impact on chip design.
Published on February 5th,  2018 by Ed Sperling

Testing Analog Chips
Increasing numbers of analog components could help perk up this market after years of steady but sleepy growth.
Published on February 5th,  2018 by Jeff Dorsch

Packaging Challenges For 2018
Shortages, pricing pressures, rising investments and more packaging options add up to an interesting year for OSATs.
Published on January 8th,  2018 by Mark LaPedus

More Top Stories »



Round Tables

2.5D Surprises And Alternatives
First of two parts: Cost and supply chain issues remain as advanced packaging begins to ramp.
Published on October 20th,  2016 by Ed Sperling

Stacked Die Changes
Experts at the table, part 3: How mature are high-speed interconnects and what hurdles remain for widespread adoption.
Published on September 21st,  2016 by Ed Sperling

Stacked Die Changes
Experts at the table, part 2: Different coefficients of thermal expansion cause warpage problems; known good die issues.
Published on September 15th,  2016 by Ed Sperling

Stacked Die Changes
Experts at the table, part 1: There are new and better options for packaging chips together as the semiconductor industry begins to figure out what...
Published on July 27th,  2016 by Ed Sperling

More Roundtables »



Multimedia

Tech Talk: System In Package
Why advanced packaging is so important for autonomous driving and the semiconductor industry.
Published on June 5th,  2017 by Ed Sperling

Tech Talk: 2.5D Issues
How ready is this packaging approach and what problems remain?
Published on February 25th,  2016 by Ed Sperling

Tech Talk: 14nm And Stacked Die
Why the 14nm node will be long lived, and how it will be used in 2.5D and 3D-IC packages.
Published on November 11th,  2015 by Ed Sperling

Tech Talk: 2.5D Stacked Die
What's the real motivation behind stacking die?
Published on November 20th,  2013 by Ed Sperling

More Multimedia »



See All Posts in Packaging and Test »

Latest Blogs

Editor's Note

The Race To Mass Customization
Why the next phase of advanced packaging is so important.
April 9, 2018
by Ed Sperling
All About Test

Xcerra’s Stock Buoyed by Busted Deal
Investors are enthusiastic for its shares.
by Jeff Dorsch
Material Science

The Problem With Spin-On Carbon Materials
How to solve the breakdown of polymers at high temperatures.
by Runhui Huang
Accelerating Design & Test

5G New Radio Signal Design
What’s in the new standard, how it differs from 4G LTE, and why it matters.
March 5, 2018
by David Vye
The Human Machine Interface

Better Living Through Microelectronics
From energy harvesting to prosthetics, semiconductor technologies have the po...
by Judy Davies
The Connected Perspective

2017: A Good Year for ATE
Test equipment sales were up, and so were the share prices of ATE stocks.
January 8, 2018
by Jeff Dorsch
Inside Big Data

Is It Safe To Assume That All “Passed” Die Ar...
Detecting tricky test escapes and preventing defective parts from getting int...
October 9, 2017
by Guy Cortez
EDA For Manufacturability

Crossing The Chasm: Uniting SoC And Package Verification
EDA companies, OSATs, and foundries must collaborate to ensure wafer-level pa...
March 6, 2017
by Tarek Ramadan

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

What Happened To Nanoimprint Litho?

Next-gen lithography technology resurfaces for a variety of tasks.

by Mark LaPedus

Get Ready For Integrated Silicon Photonics

This more than Moore technology is still ramping up, and problems need to be solved, but it could lead to some fundamental changes.

by Brian Bailey

When AI Goes Awry

So far there are no tools and no clear methodology to eliminating bugs. That would require understanding what an AI bug actually is.

by Ed Sperling

Embedded Die Packaging Emerges

Why this technology approach is suddenly getting attention, and what hurdles still remain.

by Mark LaPedus

New Shifts In Automotive Design

How electric vehicles, autonomous driving and car sharing are impacting chip design.

by Ann Steffora Mutschler

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2018 SMG   |  Terms of Service  |  Privacy Policy