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Packaging

• Chiplet-to-Chiplet Gateway Architecture, A C2C Interface Bridging Two Chiplet Protocols (Peter Grünberg, Jülich Supercomputing Centre)

  Published on May 31, 2025

• Transformation Of 2D-ICs Into 3D-ICs Using Shuttle Chips From Multi-Project Wafers (Tohoku University)

  Published on May 20, 2025

• Floorplanning Method For Reducing Thermally-Induced Structural Stress In Chiplet Packages (Penn State, Intel, ASU et al.)

  Published on May 14, 2025

• Optimizing End-to-End Communication And Workload Partitioning In MCM Accelerators (Georgia Tech)

  Published on May 3, 2025

• Inter-Chiplet Interconnect Topologies On Organic And Glass Substrates

  Published on April 29, 2025

• On-Chiplet Framework for Verifying Physical Security and Integrity of Adjacent Chiplets

  Published on April 29, 2025

• Challenges of Chiplet Placement And Routing Optimization (KAIST)

  Published on April 23, 2025

• Board-Level Packaging Method For Device Encapsulation To Enable Water Immersion Cooling

  Published on April 14, 2025

• Study Of Multi-Die And Multi-Technology Floorplanning (Texas A&M, Duke)

  Published on April 5, 2025

• Evaluation Tool For The Cost Impacts Of Chiplet-Specific Design Choices

  Published on March 25, 2025
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