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Packaging

• 3DICs: Atomic-Scale Behavior of Electromigration in Cu−Cu Joints (NYCU, ITRI)

  Published on August 5, 2025

• Challenges And Outlook of Photonic-Integrated Circuit Packaging (Hanyang Univ.)

  Published on August 1, 2025

• Statistical BER Analysis For Two Types Of Communication Systems In Chiplet Integration (TSMC)

  Published on August 1, 2025

• Nanoimprint-Based Dielectric Patterning for Fine-Pitch Hybrid Bonding (Seoul National Univ. of Science and Technology)

  Published on July 30, 2025

• Examination Of Thermal Issues Related to Hybrid Bonding of 3D-Stacked HBM

  Published on July 16, 2025

• Development and Deployment of 2.5D Multi-Foundry Chiplet Solution Scaling Beyond Multi-Reticle Approaches (Intel)

  Published on July 3, 2025

• HBM Roadmap: Next-Gen High-Bandwidth Memory Architectures (KAIST’s TERALAB)

  Published on June 16, 2025

• Chiplet-to-Chiplet Gateway Architecture, A C2C Interface Bridging Two Chiplet Protocols (Peter Grünberg, Jülich Supercomputing Centre)

  Published on May 31, 2025

• Transformation Of 2D-ICs Into 3D-ICs Using Shuttle Chips From Multi-Project Wafers (Tohoku University)

  Published on May 20, 2025

• Floorplanning Method For Reducing Thermally-Induced Structural Stress In Chiplet Packages (Penn State, Intel, ASU et al.)

  Published on May 14, 2025
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