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AI/ML/DL
Electrostatic effects
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AI/ML/DL
Changes In AI SoCs
Software In Inference Accelerators
The MLPerf Benchmark
Bridging Math & Engineering In ML
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Electrostatic effects
Electromagnetic Challenges In High-Speed Designs
Multi-Physics At 5/3nm
Thermal Impact On Reliability At 7/5nm
Aging Effects
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Communication
How 5G Affects Test
New Challenges In Testing 5G Devices
Ensuring A 5G Design Is Viable
Compressing High-Bandwidth Video
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Memory
High-Performance Memory For AI And HPC
Enterprise-Class DRAM Reliability
GDDR6 Drilldown: Applications, Tradeoffs And Specs
Memory Subsystems In Edge Inferencing Chips
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Architectures
Making Sense Of Inferencing Processors
The New CXL Standard
ML Inferencing At The Edge
Latency Under Load: HBM2 vs. GDDR6
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Packaging
CXL Vs. CCIX
Thermal Challenges In Advanced Packaging
GDDR6 – HBM2 Tradeoffs
2.5D, 3D Power Integrity
The Case For Chiplets
Variation At 10/7nm
The Next Big Chip Companies
Using High-Bandwidth Memory (HBM)
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Manufacturing & Test
EDA In The Cloud
Improving Functional Safety In Chips
Scan Diagnosis
Testing Autonomous And Semi-Autonomous Vehicles
How To Ensure Reliability
Using Digital Twins and DL In Lithography
Using Machine Learning To Break Down Silos
How 5G Affects Test
Inverse Lithography Technology
New Challenges In Testing 5G Devices
Improving Quality Through Data Analytics
Manufacturing Printed Sensors
Process Window Optimization
Changes In Smart Manufacturing
Advanced Process Control
Using ML For Post-Silicon Validation
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Power & Performance
High-Performance Memory For AI And HPC
Enterprise-Class DRAM Reliability
Improving Circuit Reliability
Reliability In Automotive Chips
Where Timing And Voltage Intersect
Tradeoffs In Embedded Vision SoCs
Thermal Guardbanding
How Chips Age
Thermal Challenges In Advanced Packaging
Electromagnetic Challenges In High-Speed Designs
Die-To-Die Connectivity
Reducing Data At The Source
Thermal Challenges And Moore’s Law
Where Is The Edge?
Smart NiCs
Inferencing At The Edge
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Design & Verification
Building A Safety Verification Flow
Speeding Up Verification Using SystemC
Timing Closure At 7/5nm
Visualizing Differences In Analog Design
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Automotive
Building A Safety Verification Flow
Improving Circuit Reliability
What’s In Your IP?
Understanding SLAM (Simultaneous Localization And Mapping)
Automotive Chip Design Workflow
Reliability In Automotive Chips
Changes In AI SoCs
Improving Functional Safety In Chips
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Security
What’s In Your IP?
Finding Hardware Trojans
IP Security In FPGAs
Holes In AI Security
Meltdown, Spectre And Foreshadow
Complexity’s Impact On Security
HW Security
Biz Talk: ASICS (2017)
Mobile Security Part 2 (2015)
Mobile Security Part 1 (2015)
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