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Design & Verification

• Open-Source RISC-V Cores: Analysis Of Scalar and Superscalar Architectures And Out-Of-Order Machines

  Published on June 5, 2025

• Hardware-Oriented Analysis of Multi-Head Latent Attention (MLA) in DeepSeek-V3 (KU Leuven)

  Published on June 4, 2025

• Customizing An LLM Tailored Specifically For VHDL Code And Design Of High Performance Processors (IBM)

  Published on June 3, 2025

• Arithmetic Intensity In Decoding: A Hardware-Efficient Perspective (Princeton University)

  Published on June 3, 2025

• Roadmap for AI HW Development, With The Role of Photonic Chips In Supporting Future LLMs (CUHK, NUS, UIUC, Berkeley)

  Published on June 1, 2025

• SRAM Cell Scaling With Monolithic 3D Integration Of 2D FETs (Penn State)

  Published on June 1, 2025

• Chiplet-to-Chiplet Gateway Architecture, A C2C Interface Bridging Two Chiplet Protocols (Peter Grünberg, Jülich Supercomputing Centre)

  Published on May 31, 2025

• Offline RL Framework That Dynamically Controls The GPU Clock And Server Fan Speed To Optimize Power Consumption And Computation Time (KAIST)

  Published on May 31, 2025

• Electrical Properties of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts (NYCU)

  Published on May 31, 2025

• A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)

  Published on May 31, 2025
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